From 85f067780a9f00503a5b6c21904565195f50282c Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 19 Sep 2013 02:08:10 +0000 Subject: [PATCH] [ARM] Reenable flush per instruction with FPR cache. Something is still very wrong. --- Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp index 8b11840682..c7cdb81d21 100644 --- a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp +++ b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp @@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo BKPT(0x7777); } JitArmTables::CompileInstruction(ops[i]); + fpr.Flush(); if (js.memcheck && (opinfo->flags & FL_LOADSTORE)) { // Don't do this yet