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Merge pull request #1404 from Sonicadvance1/fix-ARMv7 

Fixes some ARMv7 regressions.
This commit is contained in:
Ryan Houdek 2014-10-27 05:15:17 -06:00
parent 043bd710a0 0fbd5248ca
commit 81dda593cd
3 changed files with 6 additions and 14 deletions
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6
Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp
View File

@ -20,7 +20,6 @@ using namespace ArmGen;
void JitArm::sc(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
gpr.Flush();
fpr.Flush();
@ -39,7 +38,6 @@ void JitArm::sc(UGeckoInstruction inst)
void JitArm::rfi(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
gpr.Flush();
fpr.Flush();
@ -86,7 +84,6 @@ void JitArm::rfi(UGeckoInstruction inst)
void JitArm::bx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
// We must always process the following sentence
// even if the blocks are merged by PPCAnalyst::Flatten().
if (inst.LK)
@ -133,7 +130,6 @@ void JitArm::bx(UGeckoInstruction inst)
void JitArm::bcx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
// USES_CR
ARMReg rA = gpr.GetReg();
@ -193,7 +189,6 @@ void JitArm::bcx(UGeckoInstruction inst)
void JitArm::bcctrx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
// bcctrx doesn't decrement and/or test CTR
_dbg_assert_msg_(POWERPC, inst.BO_2 & BO_DONT_DECREMENT_FLAG, "bcctrx with decrement and test CTR option is invalid!");
@ -259,7 +254,6 @@ void JitArm::bcctrx(UGeckoInstruction inst)
void JitArm::bclrx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITBranchOff);
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();

13
Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp
View File

@ -570,10 +570,10 @@ void JitArm::arith(UGeckoInstruction inst)
ANDS(RA, RS, RB);
break;
case 40: // subfx
gpr.BindToRegister(d, d == s || d == b);
gpr.BindToRegister(d, d == b || d == a);
RD = gpr.R(d);
RA = gpr.R(a);
RB = gpr.R(b);
RA = gpr.R(a);
SUBS(RD, RB, RA);
break;
case 60:
@ -654,7 +654,7 @@ void JitArm::arith(UGeckoInstruction inst)
RA = gpr.R(a);
RS = gpr.R(s);
RB = gpr.R(b);
LSRS(RA, RS, RB);
LSRS(RA, RS, RB);
break;
case 792:
dest = a;
@ -662,7 +662,7 @@ void JitArm::arith(UGeckoInstruction inst)
RA = gpr.R(a);
RS = gpr.R(s);
RB = gpr.R(b);
ASRS(RA, RS, RB);
ASRS(RA, RS, RB);
break;
case 10: // addcx
case 266:
@ -841,8 +841,8 @@ void JitArm::negx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
gpr.BindToRegister(inst.RD, inst.RD == inst.RA);
ARMReg RA = gpr.R(inst.RA);
ARMReg RD = gpr.R(inst.RD);
ARMReg RA = gpr.R(inst.RA);
RSB(RD, RA, 0);
if (inst.Rc)
@ -860,7 +860,6 @@ void JitArm::rlwimix(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg rA = gpr.GetReg();
@ -883,7 +882,6 @@ void JitArm::rlwinmx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg rA = gpr.GetReg();
@ -904,7 +902,6 @@ void JitArm::rlwnmx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
u32 mask = Helper_Mask(inst.MB,inst.ME);
gpr.BindToRegister(inst.RA, inst.RA == inst.RS || inst.RA == inst.RB);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg RB = gpr.R(inst.RB);

1
Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp
View File

@ -250,6 +250,7 @@ ARMReg ArmRegCache::BindToRegister(u32 preg, bool doLoad, bool kill_imm)
else
{
u8 a = regs[preg].GetRegIndex();
ArmCRegs[a].LastLoad = 0;
return ArmCRegs[a].Reg;
}
}