From 484fc392d69c458b84581d1886903569dd2a7c1f Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 25 Oct 2014 20:34:11 -0500 Subject: [PATCH 1/3] Fixes minor bug in the ARMv7 register cache. Makes sure our register we are binding doesn't get unloaded immediately. --- Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp b/Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp index e8bc5bb0bf..fc057fdc9e 100644 --- a/Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp +++ b/Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp @@ -250,6 +250,7 @@ ARMReg ArmRegCache::BindToRegister(u32 preg, bool doLoad, bool kill_imm) else { u8 a = regs[preg].GetRegIndex(); + ArmCRegs[a].LastLoad = 0; return ArmCRegs[a].Reg; } } From 17f352e2aa1847fef1b3a73bf48ff9cc5e7cd390 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 25 Oct 2014 20:36:29 -0500 Subject: [PATCH 2/3] Fixes some overzealous optimizations from ARMv7 BindToRegister. We can't do it in rlw and friends. subfx had an inccorect check. Minor whitespace and reordering. --- .../Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp index 533615a880..e3afe530f6 100644 --- a/Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp @@ -570,10 +570,10 @@ void JitArm::arith(UGeckoInstruction inst) ANDS(RA, RS, RB); break; case 40: // subfx - gpr.BindToRegister(d, d == s || d == b); + gpr.BindToRegister(d, d == b || d == a); RD = gpr.R(d); - RA = gpr.R(a); RB = gpr.R(b); + RA = gpr.R(a); SUBS(RD, RB, RA); break; case 60: @@ -654,7 +654,7 @@ void JitArm::arith(UGeckoInstruction inst) RA = gpr.R(a); RS = gpr.R(s); RB = gpr.R(b); - LSRS(RA, RS, RB); + LSRS(RA, RS, RB); break; case 792: dest = a; @@ -662,7 +662,7 @@ void JitArm::arith(UGeckoInstruction inst) RA = gpr.R(a); RS = gpr.R(s); RB = gpr.R(b); - ASRS(RA, RS, RB); + ASRS(RA, RS, RB); break; case 10: // addcx case 266: @@ -841,8 +841,8 @@ void JitArm::negx(UGeckoInstruction inst) JITDISABLE(bJITIntegerOff); gpr.BindToRegister(inst.RD, inst.RD == inst.RA); - ARMReg RA = gpr.R(inst.RA); ARMReg RD = gpr.R(inst.RD); + ARMReg RA = gpr.R(inst.RA); RSB(RD, RA, 0); if (inst.Rc) @@ -860,7 +860,6 @@ void JitArm::rlwimix(UGeckoInstruction inst) JITDISABLE(bJITIntegerOff); u32 mask = Helper_Mask(inst.MB,inst.ME); - gpr.BindToRegister(inst.RA, inst.RA == inst.RS); ARMReg RA = gpr.R(inst.RA); ARMReg RS = gpr.R(inst.RS); ARMReg rA = gpr.GetReg(); @@ -883,7 +882,6 @@ void JitArm::rlwinmx(UGeckoInstruction inst) JITDISABLE(bJITIntegerOff); u32 mask = Helper_Mask(inst.MB,inst.ME); - gpr.BindToRegister(inst.RA, inst.RA == inst.RS); ARMReg RA = gpr.R(inst.RA); ARMReg RS = gpr.R(inst.RS); ARMReg rA = gpr.GetReg(); @@ -904,7 +902,6 @@ void JitArm::rlwnmx(UGeckoInstruction inst) JITDISABLE(bJITIntegerOff); u32 mask = Helper_Mask(inst.MB,inst.ME); - gpr.BindToRegister(inst.RA, inst.RA == inst.RS || inst.RA == inst.RB); ARMReg RA = gpr.R(inst.RA); ARMReg RS = gpr.R(inst.RS); ARMReg RB = gpr.R(inst.RB); From 0fbd5248cacaae1bae1fc442ad59dbfceeb3ad12 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 25 Oct 2014 20:38:44 -0500 Subject: [PATCH 3/3] Fixes a potential crash on the ARMv7 JIT if someone disables the entire JIT in the debugger. We can't disable branches in the JITs. Make sure they don't become disabled if someone tries to disable the full JIT. --- Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp b/Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp index cc222cce70..dd4fa2d7a7 100644 --- a/Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp +++ b/Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp @@ -20,7 +20,6 @@ using namespace ArmGen; void JitArm::sc(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); gpr.Flush(); fpr.Flush(); @@ -39,7 +38,6 @@ void JitArm::sc(UGeckoInstruction inst) void JitArm::rfi(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); gpr.Flush(); fpr.Flush(); @@ -86,7 +84,6 @@ void JitArm::rfi(UGeckoInstruction inst) void JitArm::bx(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); // We must always process the following sentence // even if the blocks are merged by PPCAnalyst::Flatten(). if (inst.LK) @@ -133,7 +130,6 @@ void JitArm::bx(UGeckoInstruction inst) void JitArm::bcx(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); // USES_CR ARMReg rA = gpr.GetReg(); @@ -193,7 +189,6 @@ void JitArm::bcx(UGeckoInstruction inst) void JitArm::bcctrx(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); // bcctrx doesn't decrement and/or test CTR _dbg_assert_msg_(POWERPC, inst.BO_2 & BO_DONT_DECREMENT_FLAG, "bcctrx with decrement and test CTR option is invalid!"); @@ -259,7 +254,6 @@ void JitArm::bcctrx(UGeckoInstruction inst) void JitArm::bclrx(UGeckoInstruction inst) { INSTRUCTION_START - JITDISABLE(bJITBranchOff); ARMReg rA = gpr.GetReg(); ARMReg rB = gpr.GetReg();