DSP: Eliminate some magic values related to the CR register
Makes some values more immediately readable.
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3f68aceaca
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@ -161,7 +161,7 @@ bool SDSP::Initialize(const DSPInitOptions& opts)
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r.sr |= SR_INT_ENABLE;
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r.sr |= SR_INT_ENABLE;
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r.sr |= SR_EXT_INT_ENABLE;
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r.sr |= SR_EXT_INT_ENABLE;
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cr = 0x804;
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cr = CR_INIT | CR_HALT;
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InitializeIFX();
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InitializeIFX();
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// Mostly keep IRAM write protected. We unprotect only when DMA-ing
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// Mostly keep IRAM write protected. We unprotect only when DMA-ing
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// in new ucodes.
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// in new ucodes.
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@ -181,9 +181,11 @@ enum class StackRegister
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// See HW/DSP.cpp.
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// See HW/DSP.cpp.
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enum : u32
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enum : u32
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{
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{
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CR_RESET = 0x0001,
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CR_EXTERNAL_INT = 0x0002,
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CR_EXTERNAL_INT = 0x0002,
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CR_HALT = 0x0004,
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CR_HALT = 0x0004,
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CR_INIT = 0x0400
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CR_INIT_CODE = 0x0400,
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CR_INIT = 0x0800
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};
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};
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// SR bits
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// SR bits
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@ -122,7 +122,7 @@ void Interpreter::rti(const UDSPInstruction)
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void Interpreter::halt(const UDSPInstruction)
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void Interpreter::halt(const UDSPInstruction)
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{
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{
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auto& state = m_dsp_core.DSPState();
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auto& state = m_dsp_core.DSPState();
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state.cr |= 0x4;
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state.cr |= CR_HALT;
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state.pc--;
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state.pc--;
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}
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}
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@ -201,7 +201,7 @@ void Interpreter::WriteCR(u16 val)
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{
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{
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL RESET");
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL RESET");
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m_dsp_core.Reset();
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m_dsp_core.Reset();
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val &= ~1;
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val &= ~CR_RESET;
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}
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}
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// init
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// init
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else if (val == 4)
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else if (val == 4)
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@ -210,7 +210,7 @@ void Interpreter::WriteCR(u16 val)
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// OSInitAudioSystem ucode should send this mail - not DSP core itself
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// OSInitAudioSystem ucode should send this mail - not DSP core itself
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT");
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT");
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m_dsp_core.SetInitHax(true);
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m_dsp_core.SetInitHax(true);
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val |= 0x800;
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val |= CR_INIT;
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}
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}
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// update cr
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// update cr
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@ -223,11 +223,11 @@ u16 Interpreter::ReadCR()
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if ((state.pc & 0x8000) != 0)
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if ((state.pc & 0x8000) != 0)
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{
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{
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state.cr |= 0x800;
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state.cr |= CR_INIT;
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}
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}
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else
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else
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{
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{
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state.cr &= ~0x800;
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state.cr &= ~CR_INIT;
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}
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}
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return state.cr;
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return state.cr;
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@ -273,9 +273,9 @@ void DSPEmitter::rti(const UDSPInstruction opc)
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// HALT
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// HALT
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// 0000 0000 0020 0001
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// 0000 0000 0020 0001
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// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
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// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
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void DSPEmitter::halt(const UDSPInstruction opc)
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void DSPEmitter::halt(const UDSPInstruction)
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{
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{
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OR(16, M_SDSP_cr(), Imm16(4));
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OR(16, M_SDSP_cr(), Imm16(CR_HALT));
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// g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
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// g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
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dsp_reg_load_stack(StackRegister::Call);
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dsp_reg_load_stack(StackRegister::Call);
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MOV(16, M_SDSP_pc(), R(DX));
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MOV(16, M_SDSP_pc(), R(DX));
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