diff --git a/Source/Core/Core/DSP/DSPCore.cpp b/Source/Core/Core/DSP/DSPCore.cpp
index 39618d5621..2385f534c1 100644
--- a/Source/Core/Core/DSP/DSPCore.cpp
+++ b/Source/Core/Core/DSP/DSPCore.cpp
@@ -161,7 +161,7 @@ bool SDSP::Initialize(const DSPInitOptions& opts)
   r.sr |= SR_INT_ENABLE;
   r.sr |= SR_EXT_INT_ENABLE;
 
-  cr = 0x804;
+  cr = CR_INIT | CR_HALT;
   InitializeIFX();
   // Mostly keep IRAM write protected. We unprotect only when DMA-ing
   // in new ucodes.
diff --git a/Source/Core/Core/DSP/DSPCore.h b/Source/Core/Core/DSP/DSPCore.h
index 719e6a02c8..ea723b580c 100644
--- a/Source/Core/Core/DSP/DSPCore.h
+++ b/Source/Core/Core/DSP/DSPCore.h
@@ -181,9 +181,11 @@ enum class StackRegister
 // See HW/DSP.cpp.
 enum : u32
 {
+  CR_RESET = 0x0001,
   CR_EXTERNAL_INT = 0x0002,
   CR_HALT = 0x0004,
-  CR_INIT = 0x0400
+  CR_INIT_CODE = 0x0400,
+  CR_INIT = 0x0800
 };
 
 // SR bits
diff --git a/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp b/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp
index 9e263a73cf..7a6b7cb517 100644
--- a/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp
+++ b/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp
@@ -122,7 +122,7 @@ void Interpreter::rti(const UDSPInstruction)
 void Interpreter::halt(const UDSPInstruction)
 {
   auto& state = m_dsp_core.DSPState();
-  state.cr |= 0x4;
+  state.cr |= CR_HALT;
   state.pc--;
 }
 
diff --git a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
index 70ea39b8f2..a9aac9d92c 100644
--- a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
+++ b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
@@ -201,7 +201,7 @@ void Interpreter::WriteCR(u16 val)
   {
     INFO_LOG_FMT(DSPLLE, "DSP_CONTROL RESET");
     m_dsp_core.Reset();
-    val &= ~1;
+    val &= ~CR_RESET;
   }
   // init
   else if (val == 4)
@@ -210,7 +210,7 @@ void Interpreter::WriteCR(u16 val)
     // OSInitAudioSystem ucode should send this mail - not DSP core itself
     INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT");
     m_dsp_core.SetInitHax(true);
-    val |= 0x800;
+    val |= CR_INIT;
   }
 
   // update cr
@@ -223,11 +223,11 @@ u16 Interpreter::ReadCR()
 
   if ((state.pc & 0x8000) != 0)
   {
-    state.cr |= 0x800;
+    state.cr |= CR_INIT;
   }
   else
   {
-    state.cr &= ~0x800;
+    state.cr &= ~CR_INIT;
   }
 
   return state.cr;
diff --git a/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp b/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp
index 664ce367c6..6a132285fe 100644
--- a/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp
+++ b/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp
@@ -273,9 +273,9 @@ void DSPEmitter::rti(const UDSPInstruction opc)
 // HALT
 // 0000 0000 0020 0001
 // Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
-void DSPEmitter::halt(const UDSPInstruction opc)
+void DSPEmitter::halt(const UDSPInstruction)
 {
-  OR(16, M_SDSP_cr(), Imm16(4));
+  OR(16, M_SDSP_cr(), Imm16(CR_HALT));
   //	g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
   dsp_reg_load_stack(StackRegister::Call);
   MOV(16, M_SDSP_pc(), R(DX));