commit
5e3a79823c
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@ -3236,6 +3236,10 @@ void ARM64FloatEmitter::FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn)
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{
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{
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Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0xF, Rd, Rn);
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Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0xF, Rd, Rn);
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}
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}
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void ARM64FloatEmitter::FRECPE(u8 size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(IsQuad(Rd), 0, 2 | (size >> 6), 0x1D, Rd, Rn);
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}
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void ARM64FloatEmitter::FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn)
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void ARM64FloatEmitter::FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn)
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{
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{
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Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0x1D, Rd, Rn);
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Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0x1D, Rd, Rn);
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@ -992,6 +992,7 @@ public:
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void FDIV(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FDIV(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FRECPE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void NOT(ARM64Reg Rd, ARM64Reg Rn);
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void NOT(ARM64Reg Rd, ARM64Reg Rn);
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@ -169,7 +169,8 @@ void JitArm64::ps_res(UGeckoInstruction inst)
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ARM64Reg VB = fpr.R(b, type);
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ARM64Reg VB = fpr.R(b, type);
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ARM64Reg VD = fpr.RW(d, type);
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ARM64Reg VD = fpr.RW(d, type);
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m_float_emit.FRSQRTE(size, reg_encoder(VD), reg_encoder(VB));
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// FIXME: implement the same LUT as in the interpreter
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m_float_emit.FRECPE(size, reg_encoder(VD), reg_encoder(VB));
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fpr.FixSinglePrecision(d);
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fpr.FixSinglePrecision(d);
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}
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}
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