From c54c49714d09b2515c7f6b080f5a13c405ecd22a Mon Sep 17 00:00:00 2001 From: Tillmann Karras Date: Wed, 3 May 2017 07:52:26 +0100 Subject: [PATCH 1/2] Arm64Emitter: add FRECPE --- Source/Core/Common/Arm64Emitter.cpp | 4 ++++ Source/Core/Common/Arm64Emitter.h | 1 + 2 files changed, 5 insertions(+) diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index 6453f29e05..f719d9aef6 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -3236,6 +3236,10 @@ void ARM64FloatEmitter::FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn) { Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0xF, Rd, Rn); } +void ARM64FloatEmitter::FRECPE(u8 size, ARM64Reg Rd, ARM64Reg Rn) +{ + Emit2RegMisc(IsQuad(Rd), 0, 2 | (size >> 6), 0x1D, Rd, Rn); +} void ARM64FloatEmitter::FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn) { Emit2RegMisc(IsQuad(Rd), 1, 2 | (size >> 6), 0x1D, Rd, Rn); diff --git a/Source/Core/Common/Arm64Emitter.h b/Source/Core/Common/Arm64Emitter.h index 143325f531..fa77737161 100644 --- a/Source/Core/Common/Arm64Emitter.h +++ b/Source/Core/Common/Arm64Emitter.h @@ -992,6 +992,7 @@ public: void FDIV(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void FNEG(u8 size, ARM64Reg Rd, ARM64Reg Rn); + void FRECPE(u8 size, ARM64Reg Rd, ARM64Reg Rn); void FRSQRTE(u8 size, ARM64Reg Rd, ARM64Reg Rn); void FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm); void NOT(ARM64Reg Rd, ARM64Reg Rn); From 5c93c98c058a7c4daa9a04cc2217ca33a2e35045 Mon Sep 17 00:00:00 2001 From: Tillmann Karras Date: Wed, 3 May 2017 08:01:28 +0100 Subject: [PATCH 2/2] JitArm64: fix ps_res --- Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp index 975a0f6f77..93306bf5a4 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp @@ -169,7 +169,8 @@ void JitArm64::ps_res(UGeckoInstruction inst) ARM64Reg VB = fpr.R(b, type); ARM64Reg VD = fpr.RW(d, type); - m_float_emit.FRSQRTE(size, reg_encoder(VD), reg_encoder(VB)); + // FIXME: implement the same LUT as in the interpreter + m_float_emit.FRECPE(size, reg_encoder(VD), reg_encoder(VB)); fpr.FixSinglePrecision(d); }