Improve context structure handling on non-Windows.
Instead of copying data into and out of a fake CONTEXT structure with only a few entries, use the platform specific structure directly with a typedef and macros. This is needed because fastmem writes need to be able to access any register from BackPatch. It adds a fair number of repetitive defines, but it's better than the alternative.
This commit is contained in:
comex
parent
4cdce55615
commit
29dc253fde
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@ -81,11 +81,9 @@ void sigsegv_handler(int signal, siginfo_t *info, void *raw_context)
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u32 em_address = (u32)(bad_address - memspace_bottom);
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CONTEXT fake_ctx;
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fake_ctx.reg_pc = ctx->arm_pc;
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const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, em_address, &fake_ctx);
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const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, em_address, ctx);
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if (new_rip) {
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ctx->arm_pc = fake_ctx.reg_pc;
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ctx->arm_pc = (u32) new_rip;
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}
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}
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@ -80,7 +80,7 @@ bool DisamLoadStore(const u32 inst, ARMReg &rD, u8 &accessSize, bool &Store)
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const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
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{
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// TODO: This ctx needs to be filled with our information
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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SContext *ctx = (SContext *)ctx_void;
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// We need to get the destination register before we start
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u32 Value = *(u32*)codePtr;
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@ -90,7 +90,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
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if (!DisamLoadStore(Value, rD, accessSize, Store))
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{
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printf("Invalid backpatch at location 0x%08x(0x%08x)\n", ctx->reg_pc, Value);
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printf("Invalid backpatch at location 0x%08x(0x%08x)\n", ctx->CTX_PC, Value);
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exit(0);
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}
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@ -117,8 +117,8 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
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emitter.MOV(R1, R10); // Addr- 5
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emitter.BL(R14); // 6
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emitter.POP(4, R0, R1, R2, R3); // 7
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u32 newPC = ctx->reg_pc - (ARMREGOFFSET + 4 * 4);
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ctx->reg_pc = newPC;
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u32 newPC = ctx->CTX_PC - (ARMREGOFFSET + 4 * 4);
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ctx->CTX_PC = newPC;
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emitter.FlushIcache();
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return codePtr;
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}
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@ -144,7 +144,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
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emitter.MOV(R14, R0); // 6
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emitter.POP(4, R0, R1, R2, R3); // 7
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emitter.MOV(rD, R14); // 8
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ctx->reg_pc -= ARMREGOFFSET + (4 * 4);
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ctx->CTX_PC -= ARMREGOFFSET + (4 * 4);
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emitter.FlushIcache();
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return codePtr;
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}
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@ -163,7 +163,7 @@ const u8 *TrampolineCache::GetWriteTrampoline(const InstructionInfo &info)
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const u8 *Jitx86Base::BackPatch(u8 *codePtr, u32 emAddress, void *ctx_void)
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{
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#ifdef _M_X64
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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SContext *ctx = (SContext *)ctx_void;
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if (!jit->IsInCodeSpace(codePtr))
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return 0; // this will become a regular crash real soon after this
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@ -206,7 +206,7 @@ const u8 *Jitx86Base::BackPatch(u8 *codePtr, u32 emAddress, void *ctx_void)
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if (info.instructionSize < 3)
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PanicAlert("Instruction too small");
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// We entered here with a BSWAP-ed EAX. We'll have to swap it back.
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ctx->Rax = Common::swap32((u32)ctx->Rax);
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ctx->CTX_RAX = Common::swap32((u32)ctx->CTX_RAX);
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return codePtr - 2;
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}
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return 0;
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@ -10,38 +10,220 @@
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#include "x64Analyzer.h"
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#include "Thunk.h"
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// Declarations and definitions
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// ----------
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// meh.
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#if defined(_WIN32)
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#include <windows.h>
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typedef CONTEXT SContext;
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#if defined(_M_X64)
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#define CTX_RAX Rax
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#define CTX_RBX Rbx
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#define CTX_RCX Rcx
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#define CTX_RDX Rdx
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#define CTX_RDI Rdi
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#define CTX_RSI Rsi
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#define CTX_RBP Rbp
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#define CTX_RSP Rsp
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#define CTX_R8 R8
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#define CTX_R9 R9
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#define CTX_R10 R10
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#define CTX_R11 R11
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#define CTX_R12 R12
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#define CTX_R13 R13
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#define CTX_R14 R14
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#define CTX_R15 R15
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#define CTX_RIP Rip
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#elif defined(_M_IX86)
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#define CTX_EAX Eax
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#define CTX_EBX Ebx
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#define CTX_ECX Ecx
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#define CTX_EDX Edx
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#define CTX_EDI Edi
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#define CTX_ESI Esi
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#define CTX_EBP Ebp
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#define CTX_ESP Esp
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#define CTX_EIP Eip
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#else
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#error No context definition for OS
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#endif
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#elif defined(__APPLE__)
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#include <mach/mach.h>
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#include <mach/message.h>
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#if defined(_M_X64)
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typedef x86_thread_state64_t SContext;
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#define CTX_RAX __rax
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#define CTX_RBX __rbx
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#define CTX_RCX __rcx
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#define CTX_RDX __rdx
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#define CTX_RDI __rdi
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#define CTX_RSI __rsi
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#define CTX_RBP __rbp
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#define CTX_RSP __rsp
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#define CTX_R8 __r8
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#define CTX_R9 __r9
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#define CTX_R10 __r10
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#define CTX_R11 __r11
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#define CTX_R12 __r12
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#define CTX_R13 __r13
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#define CTX_R14 __r14
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#define CTX_R15 __r15
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#define CTX_RIP __rip
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#elif defined(_M_IX86)
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typedef x86_thread_state_t SContext;
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#define CTX_EAX __eax
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#define CTX_EBX __ebx
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#define CTX_ECX __ecx
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#define CTX_EDX __edx
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#define CTX_EDI __edi
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#define CTX_ESI __esi
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#define CTX_EBP __ebp
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#define CTX_ESP __esp
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#define CTX_EIP __eip
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#elif defined(_M_ARM)
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typedef arm_thread_state_t SContext;
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// Add others if required.
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#define CTX_PC __pc
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#else
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#error No context definition for OS
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#endif
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#elif defined(__linux__)
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#include <signal.h>
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#if defined(_M_X64)
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#include <ucontext.h>
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typedef mcontext_t SContext;
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#define CTX_RAX gregs[REG_RAX]
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#define CTX_RBX gregs[REG_RBX]
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#define CTX_RCX gregs[REG_RCX]
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#define CTX_RDX gregs[REG_RDX]
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#define CTX_RDI gregs[REG_RDI]
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#define CTX_RSI gregs[REG_RSI]
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#define CTX_RBP gregs[REG_RBP]
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#define CTX_RSP gregs[REG_RSP]
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#define CTX_R8 gregs[REG_R8]
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#define CTX_R9 gregs[REG_R9]
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#define CTX_R10 gregs[REG_R10]
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#define CTX_R11 gregs[REG_R11]
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#define CTX_R12 gregs[REG_R12]
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#define CTX_R13 gregs[REG_R13]
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#define CTX_R14 gregs[REG_R14]
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#define CTX_R15 gregs[REG_R15]
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#define CTX_RIP gregs[REG_RIP]
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#elif defined(_M_IX86)
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#include <ucontext.h>
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typedef mcontext_t SContext;
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#define CTX_EAX gregs[REG_EAX]
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#define CTX_EBX gregs[REG_EBX]
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#define CTX_ECX gregs[REG_ECX]
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#define CTX_EDX gregs[REG_EDX]
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#define CTX_EDI gregs[REG_EDI]
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#define CTX_ESI gregs[REG_ESI]
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#define CTX_EBP gregs[REG_EBP]
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#define CTX_ESP gregs[REG_ESP]
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#define CTX_EIP gregs[REG_EIP]
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#elif defined(ANDROID)
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// Add others if required.
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typedef struct sigcontext SContext;
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#define CTX_PC arm_pc
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#else
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#error No context definition for OS
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#endif
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#elif defined(__NetBSD__)
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#include <ucontext.h>
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typedef mcontext_t SContext;
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#if defined(_M_X64)
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#define CTX_RAX __gregs[_REG_RAX]
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#define CTX_RBX __gregs[_REG_RBX]
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#define CTX_RCX __gregs[_REG_RCX]
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#define CTX_RDX __gregs[_REG_RDX]
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#define CTX_RDI __gregs[_REG_RDI]
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#define CTX_RSI __gregs[_REG_RSI]
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#define CTX_RBP __gregs[_REG_RBP]
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#define CTX_RSP __gregs[_REG_RSP]
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#define CTX_R8 __gregs[_REG_R8]
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#define CTX_R9 __gregs[_REG_R9]
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#define CTX_R10 __gregs[_REG_R10]
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#define CTX_R11 __gregs[_REG_R11]
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#define CTX_R12 __gregs[_REG_R12]
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#define CTX_R13 __gregs[_REG_R13]
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#define CTX_R14 __gregs[_REG_R14]
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#define CTX_R15 __gregs[_REG_R15]
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#define CTX_RIP __gregs[_REG_RIP]
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#elif defined(_M_IX86)
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#define CTX_EAX __gregs[__REG_EAX]
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#define CTX_EBX __gregs[__REG_EBX]
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#define CTX_ECX __gregs[__REG_ECX]
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#define CTX_EDX __gregs[__REG_EDX]
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#define CTX_EDI __gregs[__REG_EDI]
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#define CTX_ESI __gregs[__REG_ESI]
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#define CTX_EBP __gregs[__REG_EBP]
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#define CTX_ESP __gregs[__REG_ESP]
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#define CTX_EIP __gregs[__REG_EIP]
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#else
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#error No context definition for OS
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#endif
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#elif defined(__FreeBSD__)
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#include <ucontext.h>
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typedef mcontext_t SContext;
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#if defined(_M_X64)
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#define CTX_RAX mc_rax
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#define CTX_RBX mc_rbx
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#define CTX_RCX mc_rcx
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#define CTX_RDX mc_rdx
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#define CTX_RDI mc_rdi
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#define CTX_RSI mc_rsi
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#define CTX_RBP mc_rbp
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#define CTX_RSP mc_rsp
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#define CTX_R8 mc_r8
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#define CTX_R9 mc_r9
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#define CTX_R10 mc_r10
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#define CTX_R11 mc_r11
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#define CTX_R12 mc_r12
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#define CTX_R13 mc_r13
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#define CTX_R14 mc_r14
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#define CTX_R15 mc_r15
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#define CTX_RIP mc_rip
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#elif defined(_M_IX86)
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#define CTX_EAX mc_eax
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#define CTX_EBX mc_ebx
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#define CTX_ECX mc_ecx
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#define CTX_EDX mc_edx
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#define CTX_EDI mc_edi
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#define CTX_ESI mc_esi
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#define CTX_EBP mc_ebp
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#define CTX_ESP mc_esp
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#define CTX_EIP mc_eip
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#else
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#error No context definition for OS
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#endif
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#endif
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// void Jit(u32 em_address);
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#ifndef _WIN32
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// A bit of a hack to get things building under linux. We manually fill in this structure as needed
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// from the real context.
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struct CONTEXT
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#if defined(_M_X64)
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#define CTX_PC CTX_RIP
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#include <stddef.h>
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static inline u64 *ContextRN(SContext* ctx, int n)
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{
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#ifdef _M_ARM
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u32 reg_pc;
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#else
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#ifdef _M_X64
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u64 Rip;
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u64 Rax;
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#else
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u32 Eip;
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u32 Eax;
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#endif
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#endif
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static const u8 offsets[] =
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{
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offsetof(SContext, CTX_RAX),
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offsetof(SContext, CTX_RCX),
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offsetof(SContext, CTX_RDX),
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offsetof(SContext, CTX_RBX),
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offsetof(SContext, CTX_RSP),
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offsetof(SContext, CTX_RBP),
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offsetof(SContext, CTX_RSI),
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offsetof(SContext, CTX_RDI),
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offsetof(SContext, CTX_R8),
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offsetof(SContext, CTX_R9),
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offsetof(SContext, CTX_R10),
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offsetof(SContext, CTX_R11),
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offsetof(SContext, CTX_R12),
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offsetof(SContext, CTX_R13),
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offsetof(SContext, CTX_R14),
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offsetof(SContext, CTX_R15)
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};
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#endif
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#if defined(_M_ARM)
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#define CONTEXT_PC(ctx) ((ctx)->reg_pc)
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#elif defined(_M_X64)
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#define CONTEXT_PC(ctx) ((ctx)->Rip)
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#else
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#define CONTEXT_PC(ctx) ((ctx)->Eip)
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return (u64 *) ((char *) ctx + offsets[n]);
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}
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#elif defined(_M_IX86)
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#define CTX_PC CTX_EIP
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#endif
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class TrampolineCache : public Gen::XCodeBlock
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@ -2,44 +2,11 @@
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#ifdef _WIN32
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#include <windows.h>
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#else
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#include <stdio.h>
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#include <signal.h>
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#ifndef ANDROID
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#include <sys/ucontext.h> // Look in here for the context definition.
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#endif
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#endif
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#ifdef __APPLE__
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#include <mach/mach.h>
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#include <mach/message.h>
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#include "Thread.h"
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#endif
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#ifdef __APPLE__
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#define CREG_RAX(ctx) (*(ctx))->__ss.__rax
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#define CREG_RIP(ctx) (*(ctx))->__ss.__rip
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#define CREG_EAX(ctx) (*(ctx))->__ss.__eax
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#define CREG_EIP(ctx) (*(ctx))->__ss.__eip
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#elif defined __FreeBSD__
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#define CREG_RAX(ctx) (ctx)->mc_rax
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#define CREG_RIP(ctx) (ctx)->mc_rip
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#define CREG_EAX(ctx) (ctx)->mc_eax
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#define CREG_EIP(ctx) (ctx)->mc_eip
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#elif defined __linux__
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#define CREG_RAX(ctx) (ctx)->gregs[REG_RAX]
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#define CREG_RIP(ctx) (ctx)->gregs[REG_RIP]
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#define CREG_EAX(ctx) (ctx)->gregs[REG_EAX]
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#define CREG_EIP(ctx) (ctx)->gregs[REG_EIP]
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#elif defined __NetBSD__
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#define CREG_RAX(ctx) (ctx)->__gregs[_REG_RAX]
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#define CREG_RIP(ctx) (ctx)->__gregs[_REG_RIP]
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#define CREG_EAX(ctx) (ctx)->__gregs[_REG_EAX]
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#define CREG_EIP(ctx) (ctx)->__gregs[_REG_EIP]
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#endif
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#include <vector>
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#include "Common.h"
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@ -73,9 +40,9 @@ void print_trace(const char * msg)
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}
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#endif
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bool DoFault(u64 bad_address, CONTEXT *ctx)
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bool DoFault(u64 bad_address, SContext *ctx)
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{
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if (!JitInterface::IsInCodeSpace((u8*) CONTEXT_PC(ctx)))
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if (!JitInterface::IsInCodeSpace((u8*) ctx->CTX_PC))
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{
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// Let's not prevent debugging.
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return false;
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@ -93,10 +60,10 @@ bool DoFault(u64 bad_address, CONTEXT *ctx)
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return false;
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}
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u32 em_address = (u32)(bad_address - memspace_bottom);
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const u8 *new_pc = jit->BackPatch((u8*) CONTEXT_PC(ctx), em_address, ctx);
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const u8 *new_pc = jit->BackPatch((u8*) ctx->CTX_PC, em_address, ctx);
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if (new_pc)
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{
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CONTEXT_PC(ctx) = (u64) new_pc;
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ctx->CTX_PC = (u64) new_pc;
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}
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return true;
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@ -244,14 +211,8 @@ void ExceptionThread(mach_port_t port)
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}
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x86_thread_state64_t *state = (x86_thread_state64_t *) msg_in.old_state;
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CONTEXT fake_ctx;
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fake_ctx.Rax = state->__rax;
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fake_ctx.Rip = state->__rip;
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bool ok = DoFault(msg_in.code[1], &fake_ctx);
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state->__rax = fake_ctx.Rax;
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state->__rip = fake_ctx.Rip;
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bool ok = DoFault(msg_in.code[1], state);
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// Set up the reply.
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msg_out.Head.msgh_bits = MACH_MSGH_BITS(MACH_MSGH_BITS_REMOTE(msg_in.Head.msgh_bits), 0);
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@ -324,26 +285,8 @@ void sigsegv_handler(int sig, siginfo_t *info, void *raw_context)
|
|||
|
||||
// Get all the information we can out of the context.
|
||||
mcontext_t *ctx = &context->uc_mcontext;
|
||||
CONTEXT fake_ctx;
|
||||
#ifdef _M_X64
|
||||
fake_ctx.Rax = CREG_RAX(ctx);
|
||||
fake_ctx.Rip = CREG_RIP(ctx);
|
||||
#else
|
||||
fake_ctx.Eax = CREG_EAX(ctx);
|
||||
fake_ctx.Eip = CREG_EIP(ctx);
|
||||
#endif
|
||||
// assume it's not a write
|
||||
if (DoFault(bad_address, &fake_ctx))
|
||||
{
|
||||
#ifdef _M_X64
|
||||
CREG_RAX(ctx) = fake_ctx.Rax;
|
||||
CREG_RIP(ctx) = fake_ctx.Rip;
|
||||
#else
|
||||
CREG_EAX(ctx) = fake_ctx.Eax;
|
||||
CREG_EIP(ctx) = fake_ctx.Eip;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
if (!DoFault(bad_address, ctx))
|
||||
{
|
||||
// retry and crash
|
||||
signal(SIGSEGV, SIG_DFL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue