Don't define _M_IX86 on ARM(!).
Also define _M_* in a common location, and clean up code that these changes break (including DSPJit files that assume X86 yet are compiled on ARM for some reason...)
This commit is contained in:
comex
parent
a7f2160a0f
commit
4cdce55615
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@ -122,17 +122,12 @@ if(${CMAKE_SYSTEM_PROCESSOR} MATCHES "^arm")
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set(_M_GENERIC 1)
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set(_M_ARM 1)
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add_definitions(-marm -march=armv7-a)
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add_definitions(-D_M_ARM=1)
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add_definitions(-D_M_GENERIC=1)
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# Set generic options so you don't have to pass anything to cmake to build ARM
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set(USE_GLES 1)
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endif()
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if(${CMAKE_SYSTEM_PROCESSOR} MATCHES "mips")
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set(_M_GENERIC 1)
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set(_M_MIPS 1)
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add_definitions(-D_M_MIPS=1)
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add_definitions(-D_M_GENERIC=1)
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endif()
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# Set these next two lines to test generic
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@ -49,7 +49,6 @@ private:
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#include "Log.h"
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#include "CommonTypes.h"
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#include "MsgHandler.h"
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#include "CommonFuncs.h"
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#ifdef __APPLE__
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// The Darwin ABI requires that stack frames be aligned to 16-byte boundaries.
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@ -100,14 +99,24 @@ private:
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#endif
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// Windows compatibility
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#define _M_64BIT defined(_LP64) || defined(_WIN64)
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#ifndef _WIN32
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#include <limits.h>
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#define MAX_PATH PATH_MAX
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#ifdef _LP64
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#ifdef __x86_64__
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#define _M_X64 1
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#else
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#endif
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#ifdef __i386__
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#define _M_IX86 1
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#endif
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#ifdef __arm__
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#define _M_ARM 1
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#define _M_GENERIC 1
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#endif
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#ifdef __mips__
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#define _M_MIPS 1
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#define _M_GENERIC 1
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#endif
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#define __forceinline inline __attribute__((always_inline))
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#define GC_ALIGNED16(x) __attribute__((aligned(16))) x
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#define GC_ALIGNED32(x) __attribute__((aligned(32))) x
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@ -164,4 +173,6 @@ enum EMUSTATE_CHANGE
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EMUSTATE_CHANGE_STOP
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};
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#include "CommonFuncs.h"
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#endif // _COMMON_H_
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@ -14,6 +14,7 @@
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#include <cstddef>
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#include <type_traits>
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#include "Common.h"
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// Will fail to compile on a non-array:
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// TODO: make this a function when constexpr is available
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@ -3,6 +3,7 @@
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// Refer to the license.txt file included.
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#include <memory.h>
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#include "Common.h"
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#ifdef _WIN32
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#define _interlockedbittestandset workaround_ms_header_bug_platform_sdk6_set
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@ -36,7 +36,7 @@ enum DSPJitSignExtend
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#ifdef _M_X64
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#define NUMXREGS 16
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#elif _M_IX86
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#else
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#define NUMXREGS 8
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#endif
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@ -27,10 +27,10 @@ void DSPEmitter::dsp_reg_stack_push(int stack_reg)
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gpr.getFreeXReg(tmp1);
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//g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]] = g_dsp.r[DSP_REG_ST0 + stack_reg];
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MOV(16, R(tmp1), M(&g_dsp.r.st[stack_reg]));
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#ifdef _M_IX86 // All32
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MOVZX(32, 8, EAX, R(AL));
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#else
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#ifdef _M_X64
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MOVZX(64, 8, RAX, R(AL));
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#else
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MOVZX(32, 8, EAX, R(AL));
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#endif
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MOV(16, MComplex(EAX, EAX, 1,
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PtrOffset(&g_dsp.reg_stack[stack_reg][0],0)), R(tmp1));
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@ -46,10 +46,10 @@ void DSPEmitter::dsp_reg_stack_pop(int stack_reg)
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MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg]));
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X64Reg tmp1;
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gpr.getFreeXReg(tmp1);
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#ifdef _M_IX86 // All32
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MOVZX(32, 8, EAX, R(AL));
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#else
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#ifdef _M_X64
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MOVZX(64, 8, RAX, R(AL));
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#else
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MOVZX(32, 8, EAX, R(AL));
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#endif
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MOV(16, R(tmp1), MComplex(EAX, EAX, 1,
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PtrOffset(&g_dsp.reg_stack[stack_reg][0],0)));
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@ -209,17 +209,17 @@ void DSPEmitter::dsp_op_read_reg_dont_saturate(int reg, Gen::X64Reg host_dreg, D
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switch(extend)
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{
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case SIGN:
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#ifdef _M_IX86 // All32
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MOVSX(32, 16, host_dreg, R(host_dreg));
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#else
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#ifdef _M_X64
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MOVSX(64, 16, host_dreg, R(host_dreg));
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#else
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MOVSX(32, 16, host_dreg, R(host_dreg));
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#endif
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break;
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case ZERO:
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, host_dreg, R(host_dreg));
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#else
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#ifdef _M_X64
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MOVZX(64, 16, host_dreg, R(host_dreg));
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#else
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MOVZX(32, 16, host_dreg, R(host_dreg));
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#endif
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break;
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case NONE:
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@ -245,17 +245,17 @@ void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg, DSPJitSignExten
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switch(extend)
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{
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case SIGN:
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#ifdef _M_IX86 // All32
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MOVSX(32, 16, host_dreg, R(host_dreg));
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#else
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#ifdef _M_X64
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MOVSX(64, 16, host_dreg, R(host_dreg));
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#else
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MOVSX(32, 16, host_dreg, R(host_dreg));
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#endif
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break;
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case ZERO:
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, host_dreg, R(host_dreg));
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#else
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#ifdef _M_X64
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MOVZX(64, 16, host_dreg, R(host_dreg));
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#else
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MOVZX(32, 16, host_dreg, R(host_dreg));
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#endif
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break;
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case NONE:
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@ -267,11 +267,11 @@ void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg, DSPJitSignExten
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case DSP_REG_ACM1:
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{
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//we already know this is ACCM0 or ACCM1
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#ifdef _M_IX86 // All32
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gpr.readReg(reg, host_dreg, extend);
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#else
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#ifdef _M_X64
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OpArg acc_reg;
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gpr.getReg(reg-DSP_REG_ACM0+DSP_REG_ACC0_64, acc_reg);
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#else
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gpr.readReg(reg, host_dreg, extend);
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#endif
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OpArg sr_reg;
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gpr.getReg(DSP_REG_SR,sr_reg);
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@ -280,7 +280,38 @@ void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg, DSPJitSignExten
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TEST(16, sr_reg, Imm16(SR_40_MODE_BIT));
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FixupBranch not_40bit = J_CC(CC_Z, true);
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#ifdef _M_IX86 // All32
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#ifdef _M_X64
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MOVSX(64,32,host_dreg,acc_reg);
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CMP(64,R(host_dreg),acc_reg);
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FixupBranch no_saturate = J_CC(CC_Z);
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CMP(64,acc_reg,Imm32(0));
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FixupBranch negative = J_CC(CC_LE);
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MOV(64,R(host_dreg),Imm32(0x7fff));//this works for all extend modes
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FixupBranch done_positive = J();
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SetJumpTarget(negative);
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if (extend == NONE || extend == ZERO)
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MOV(64,R(host_dreg),Imm32(0x00008000));
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else
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MOV(64,R(host_dreg),Imm32(0xffff8000));
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FixupBranch done_negative = J();
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SetJumpTarget(no_saturate);
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SetJumpTarget(not_40bit);
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MOV(64, R(host_dreg), acc_reg);
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if (extend == NONE || extend == ZERO)
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SHR(64, R(host_dreg), Imm8(16));
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else
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SAR(64, R(host_dreg), Imm8(16));
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SetJumpTarget(done_positive);
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SetJumpTarget(done_negative);
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gpr.flushRegs(c);
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gpr.putReg(reg-DSP_REG_ACM0+DSP_REG_ACC0_64, false);
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#else
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DSPJitRegCache c2(gpr);
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gpr.putReg(DSP_REG_SR, false);
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X64Reg tmp1;
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@ -315,37 +346,6 @@ void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg, DSPJitSignExten
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gpr.flushRegs(c2);
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SetJumpTarget(not_40bit);
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gpr.flushRegs(c);
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#else
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MOVSX(64,32,host_dreg,acc_reg);
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CMP(64,R(host_dreg),acc_reg);
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FixupBranch no_saturate = J_CC(CC_Z);
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CMP(64,acc_reg,Imm32(0));
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FixupBranch negative = J_CC(CC_LE);
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MOV(64,R(host_dreg),Imm32(0x7fff));//this works for all extend modes
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FixupBranch done_positive = J();
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SetJumpTarget(negative);
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if (extend == NONE || extend == ZERO)
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MOV(64,R(host_dreg),Imm32(0x00008000));
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else
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MOV(64,R(host_dreg),Imm32(0xffff8000));
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FixupBranch done_negative = J();
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SetJumpTarget(no_saturate);
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SetJumpTarget(not_40bit);
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MOV(64, R(host_dreg), acc_reg);
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if (extend == NONE || extend == ZERO)
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SHR(64, R(host_dreg), Imm8(16));
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else
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SAR(64, R(host_dreg), Imm8(16));
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SetJumpTarget(done_positive);
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SetJumpTarget(done_negative);
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gpr.flushRegs(c);
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gpr.putReg(reg-DSP_REG_ACM0+DSP_REG_ACC0_64, false);
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#endif
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gpr.putReg(DSP_REG_SR, false);
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@ -612,11 +612,11 @@ void DSPEmitter::dmem_write_imm(u16 address, X64Reg value)
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switch (address >> 12)
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{
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case 0x0: // 0xxx DRAM
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.dram[address & DSP_DRAM_MASK]), R(value));
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#else
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#ifdef _M_X64
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MOV(64, R(RDX), ImmPtr(g_dsp.dram));
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MOV(16, MDisp(RDX, (address & DSP_DRAM_MASK)*2), R(value));
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#else
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MOV(16, M(&g_dsp.dram[address & DSP_DRAM_MASK]), R(value));
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#endif
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break;
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@ -720,20 +720,20 @@ void DSPEmitter::dmem_read_imm(u16 address)
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switch (address >> 12)
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{
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case 0x0: // 0xxx DRAM
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), M(&g_dsp.dram[address & DSP_DRAM_MASK]));
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#else
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#ifdef _M_X64
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MOV(64, R(RDX), ImmPtr(g_dsp.dram));
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MOV(16, R(EAX), MDisp(RDX, (address & DSP_DRAM_MASK)*2));
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#else
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MOV(16, R(EAX), M(&g_dsp.dram[address & DSP_DRAM_MASK]));
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#endif
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break;
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case 0x1: // 1xxx COEF
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), Imm16(g_dsp.coef[address & DSP_COEF_MASK]));
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#else
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#ifdef _M_X64
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MOV(64, R(RDX), ImmPtr(g_dsp.coef));
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MOV(16, R(EAX), MDisp(RDX, (address & DSP_COEF_MASK)*2));
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#else
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MOV(16, R(EAX), Imm16(g_dsp.coef[address & DSP_COEF_MASK]));
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#endif
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break;
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@ -79,7 +79,7 @@ enum
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ADDR_MASK_HW_ACCESS = 0x0c000000,
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ADDR_MASK_MEM1 = 0x20000000,
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#ifdef _M_IX86
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#ifndef _M_X64
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MEMVIEW32_MASK = 0x3FFFFFFF,
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#endif
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};
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@ -110,10 +110,10 @@ inline u8* GetCachePtr() {return m_pL1Cache;}
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inline u8* GetMainRAMPtr() {return m_pRAM;}
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inline u32 ReadFast32(const u32 _Address)
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{
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#ifdef _M_IX86
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return Common::swap32(*(u32 *)(base + (_Address & MEMVIEW32_MASK))); // ReadUnchecked_U32(_Address);
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#elif defined(_M_X64)
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#if defined(_M_X64)
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return Common::swap32(*(u32 *)(base + _Address));
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#else
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return Common::swap32(*(u32 *)(base + (_Address & MEMVIEW32_MASK))); // ReadUnchecked_U32(_Address);
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#endif
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}
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