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JitArm64: Optimize addi2r & subi2r.

This commit is contained in:
degasus 2016-10-26 21:17:29 +02:00
parent df250b84cc
commit 1df694626d
1 changed files with 20 additions and 0 deletions
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20
Source/Core/Common/Arm64Emitter.cpp
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@ -4131,10 +4131,15 @@ void ARM64XEmitter::ADDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{ {
u32 val; u32 val;
bool shift; bool shift;
u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
if (IsImmArithmetic(imm, &val, &shift)) if (IsImmArithmetic(imm, &val, &shift))
{ {
ADD(Rd, Rn, val, shift); ADD(Rd, Rn, val, shift);
} }
else if (IsImmArithmetic(imm_neg, &val, &shift))
{
SUB(Rd, Rn, val, shift);
}
else else
{ {
_assert_msg_(DYNA_REC, scratch != INVALID_REG, _assert_msg_(DYNA_REC, scratch != INVALID_REG,
@ -4149,10 +4154,15 @@ void ARM64XEmitter::ADDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{ {
u32 val; u32 val;
bool shift; bool shift;
u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
if (IsImmArithmetic(imm, &val, &shift)) if (IsImmArithmetic(imm, &val, &shift))
{ {
ADDS(Rd, Rn, val, shift); ADDS(Rd, Rn, val, shift);
} }
else if (IsImmArithmetic(imm_neg, &val, &shift))
{
SUBS(Rd, Rn, val, shift);
}
else else
{ {
_assert_msg_(DYNA_REC, scratch != INVALID_REG, _assert_msg_(DYNA_REC, scratch != INVALID_REG,
@ -4167,10 +4177,15 @@ void ARM64XEmitter::SUBI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{ {
u32 val; u32 val;
bool shift; bool shift;
u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
if (IsImmArithmetic(imm, &val, &shift)) if (IsImmArithmetic(imm, &val, &shift))
{ {
SUB(Rd, Rn, val, shift); SUB(Rd, Rn, val, shift);
} }
else if (IsImmArithmetic(imm_neg, &val, &shift))
{
ADD(Rd, Rn, val, shift);
}
else else
{ {
_assert_msg_(DYNA_REC, scratch != INVALID_REG, _assert_msg_(DYNA_REC, scratch != INVALID_REG,
@ -4185,10 +4200,15 @@ void ARM64XEmitter::SUBSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{ {
u32 val; u32 val;
bool shift; bool shift;
u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
if (IsImmArithmetic(imm, &val, &shift)) if (IsImmArithmetic(imm, &val, &shift))
{ {
SUBS(Rd, Rn, val, shift); SUBS(Rd, Rn, val, shift);
} }
else if (IsImmArithmetic(imm_neg, &val, &shift))
{
ADDS(Rd, Rn, val, shift);
}
else else
{ {
_assert_msg_(DYNA_REC, scratch != INVALID_REG, _assert_msg_(DYNA_REC, scratch != INVALID_REG,