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Jit64: addx - Emit nothing when possible 

When the destination register matches a source register, the other
source register contains zero, and overflow isn't needed, the
instruction becomes a nop and we don't need to emit anything.

We could add specialized handling for the case where overflow is needed,
but none of the titles I tried would hit this path.

Before:
83 C7 00             add         edi,0

After:
This commit is contained in:
Sintendo 2020-04-19 23:02:13 +02:00
parent f1c3ab359d
commit 1c25e6352a
1 changed files with 4 additions and 1 deletions
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5
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -1333,7 +1333,10 @@ void Jit64::addx(UGeckoInstruction inst)
if ((d == a) || (d == b)) if ((d == a) || (d == b))
{ {
RCOpArg& Rnotd = (d == a) ? Rb : Ra; RCOpArg& Rnotd = (d == a) ? Rb : Ra;
ADD(32, Rd, Rnotd); if (!Rnotd.IsZero() || inst.OE)
{
ADD(32, Rd, Rnotd);
}
} }
else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE) else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
{ {