PowerPC: Convert #defines into typed constants
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@ -1028,7 +1028,7 @@ static void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 addre
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const int tag = address >> HW_PAGE_INDEX_SHIFT;
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TLBEntry& tlbe = ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK];
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const int index = tlbe.recent == 0 && tlbe.tag[0] != TLB_TAG_INVALID;
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const int index = tlbe.recent == 0 && tlbe.tag[0] != TLBEntry::INVALID_TAG;
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tlbe.recent = index;
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tlbe.paddr[index] = PTE2.RPN << HW_PAGE_INDEX_SHIFT;
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tlbe.pte[index] = PTE2.Hex;
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@ -1040,12 +1040,12 @@ void InvalidateTLBEntry(u32 address)
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const u32 entry_index = (address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK;
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TLBEntry& tlbe = ppcState.tlb[0][entry_index];
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tlbe.tag[0] = TLB_TAG_INVALID;
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tlbe.tag[1] = TLB_TAG_INVALID;
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tlbe.tag[0] = TLBEntry::INVALID_TAG;
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tlbe.tag[1] = TLBEntry::INVALID_TAG;
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TLBEntry& tlbe_i = ppcState.tlb[1][entry_index];
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tlbe_i.tag[0] = TLB_TAG_INVALID;
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tlbe_i.tag[1] = TLB_TAG_INVALID;
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tlbe_i.tag[0] = TLBEntry::INVALID_TAG;
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tlbe_i.tag[1] = TLBEntry::INVALID_TAG;
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}
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// Page Address Translation
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@ -37,14 +37,15 @@ enum class CoreMode
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};
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// TLB cache
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#define TLB_SIZE 128
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#define NUM_TLBS 2
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#define TLB_WAYS 2
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#define TLB_TAG_INVALID 0xffffffff
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constexpr size_t TLB_SIZE = 128;
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constexpr size_t NUM_TLBS = 2;
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constexpr size_t TLB_WAYS = 2;
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struct TLBEntry
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{
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u32 tag[TLB_WAYS] = {TLB_TAG_INVALID, TLB_TAG_INVALID};
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static constexpr u32 INVALID_TAG = 0xffffffff;
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u32 tag[TLB_WAYS] = {INVALID_TAG, INVALID_TAG};
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u32 paddr[TLB_WAYS] = {};
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u32 pte[TLB_WAYS] = {};
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u8 recent = 0;
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