diff --git a/Source/Core/Core/PowerPC/MMU.cpp b/Source/Core/Core/PowerPC/MMU.cpp
index b2555d4b3a..416174a995 100644
--- a/Source/Core/Core/PowerPC/MMU.cpp
+++ b/Source/Core/Core/PowerPC/MMU.cpp
@@ -1028,7 +1028,7 @@ static void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 addre
 
   const int tag = address >> HW_PAGE_INDEX_SHIFT;
   TLBEntry& tlbe = ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK];
-  const int index = tlbe.recent == 0 && tlbe.tag[0] != TLB_TAG_INVALID;
+  const int index = tlbe.recent == 0 && tlbe.tag[0] != TLBEntry::INVALID_TAG;
   tlbe.recent = index;
   tlbe.paddr[index] = PTE2.RPN << HW_PAGE_INDEX_SHIFT;
   tlbe.pte[index] = PTE2.Hex;
@@ -1040,12 +1040,12 @@ void InvalidateTLBEntry(u32 address)
   const u32 entry_index = (address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK;
 
   TLBEntry& tlbe = ppcState.tlb[0][entry_index];
-  tlbe.tag[0] = TLB_TAG_INVALID;
-  tlbe.tag[1] = TLB_TAG_INVALID;
+  tlbe.tag[0] = TLBEntry::INVALID_TAG;
+  tlbe.tag[1] = TLBEntry::INVALID_TAG;
 
   TLBEntry& tlbe_i = ppcState.tlb[1][entry_index];
-  tlbe_i.tag[0] = TLB_TAG_INVALID;
-  tlbe_i.tag[1] = TLB_TAG_INVALID;
+  tlbe_i.tag[0] = TLBEntry::INVALID_TAG;
+  tlbe_i.tag[1] = TLBEntry::INVALID_TAG;
 }
 
 // Page Address Translation
diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h
index 3e21dbe824..83647602dd 100644
--- a/Source/Core/Core/PowerPC/PowerPC.h
+++ b/Source/Core/Core/PowerPC/PowerPC.h
@@ -37,14 +37,15 @@ enum class CoreMode
 };
 
 // TLB cache
-#define TLB_SIZE 128
-#define NUM_TLBS 2
-#define TLB_WAYS 2
-#define TLB_TAG_INVALID 0xffffffff
+constexpr size_t TLB_SIZE = 128;
+constexpr size_t NUM_TLBS = 2;
+constexpr size_t TLB_WAYS = 2;
 
 struct TLBEntry
 {
-  u32 tag[TLB_WAYS] = {TLB_TAG_INVALID, TLB_TAG_INVALID};
+  static constexpr u32 INVALID_TAG = 0xffffffff;
+
+  u32 tag[TLB_WAYS] = {INVALID_TAG, INVALID_TAG};
   u32 paddr[TLB_WAYS] = {};
   u32 pte[TLB_WAYS] = {};
   u8 recent = 0;