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PowerPC: Remove rSPR macro.

This commit is contained in:
Admiral H. Curtiss 2023-01-10 00:39:50 +01:00
parent 27ce432012
commit 0cd4a226d2
No known key found for this signature in database
GPG Key ID: F051B4C4044F33FB
4 changed files with 32 additions and 30 deletions
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4
Source/Core/Core/PowerPC/Expression.cpp
View File

@ -258,9 +258,9 @@ void Expression::SynchronizeBindings(SynchronizeDirection dir) const
break; break;
case VarBindingType::SPR: case VarBindingType::SPR:
if (dir == SynchronizeDirection::From) if (dir == SynchronizeDirection::From)
v->value = static_cast<double>(rSPR(bind->index)); v->value = static_cast<double>(PowerPC::ppcState.spr[bind->index]);
else else
rSPR(bind->index) = static_cast<u32>(static_cast<s64>(v->value)); PowerPC::ppcState.spr[bind->index] = static_cast<u32>(static_cast<s64>(v->value));
break; break;
case VarBindingType::PCtr: case VarBindingType::PCtr:
if (dir == SynchronizeDirection::From) if (dir == SynchronizeDirection::From)

55
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
View File

@ -228,9 +228,9 @@ void Interpreter::mfspr(UGeckoInstruction inst)
switch (index) switch (index)
{ {
case SPR_DEC: case SPR_DEC:
if ((rSPR(index) & 0x80000000) == 0) // We are still decrementing if ((PowerPC::ppcState.spr[index] & 0x80000000) == 0) // We are still decrementing
{ {
rSPR(index) = SystemTimers::GetFakeDecrementer(); PowerPC::ppcState.spr[index] = SystemTimers::GetFakeDecrementer();
} }
break; break;
@ -248,40 +248,40 @@ void Interpreter::mfspr(UGeckoInstruction inst)
// Currently, we always treat the buffer as not empty, as the exact behavior is unclear // Currently, we always treat the buffer as not empty, as the exact behavior is unclear
// (and games that use display lists will hang if the bit doesn't eventually become zero). // (and games that use display lists will hang if the bit doesn't eventually become zero).
if (Core::System::GetInstance().GetGPFifo().IsBNE()) if (Core::System::GetInstance().GetGPFifo().IsBNE())
rSPR(index) |= 1; PowerPC::ppcState.spr[index] |= 1;
else else
rSPR(index) &= ~1; PowerPC::ppcState.spr[index] &= ~1;
} }
break; break;
case SPR_XER: case SPR_XER:
rSPR(index) = PowerPC::GetXER().Hex; PowerPC::ppcState.spr[index] = PowerPC::GetXER().Hex;
break; break;
case SPR_UPMC1: case SPR_UPMC1:
rSPR(index) = rSPR(SPR_PMC1); PowerPC::ppcState.spr[index] = PowerPC::ppcState.spr[SPR_PMC1];
break; break;
case SPR_UPMC2: case SPR_UPMC2:
rSPR(index) = rSPR(SPR_PMC2); PowerPC::ppcState.spr[index] = PowerPC::ppcState.spr[SPR_PMC2];
break; break;
case SPR_UPMC3: case SPR_UPMC3:
rSPR(index) = rSPR(SPR_PMC3); PowerPC::ppcState.spr[index] = PowerPC::ppcState.spr[SPR_PMC3];
break; break;
case SPR_UPMC4: case SPR_UPMC4:
rSPR(index) = rSPR(SPR_PMC4); PowerPC::ppcState.spr[index] = PowerPC::ppcState.spr[SPR_PMC4];
break; break;
case SPR_IABR: case SPR_IABR:
// A strange quirk: reading back this register on hardware will always have the TE (Translation // A strange quirk: reading back this register on hardware will always have the TE (Translation
// enabled) bit set to 0 (despite the bit appearing to function normally when set). This does // enabled) bit set to 0 (despite the bit appearing to function normally when set). This does
// not apply to the DABR. // not apply to the DABR.
PowerPC::ppcState.gpr[inst.RD] = rSPR(index) & ~1; PowerPC::ppcState.gpr[inst.RD] = PowerPC::ppcState.spr[index] & ~1;
return; return;
} }
PowerPC::ppcState.gpr[inst.RD] = rSPR(index); PowerPC::ppcState.gpr[inst.RD] = PowerPC::ppcState.spr[index];
} }
void Interpreter::mtspr(UGeckoInstruction inst) void Interpreter::mtspr(UGeckoInstruction inst)
@ -295,8 +295,8 @@ void Interpreter::mtspr(UGeckoInstruction inst)
return; return;
} }
const u32 old_value = rSPR(index); const u32 old_value = PowerPC::ppcState.spr[index];
rSPR(index) = PowerPC::ppcState.gpr[inst.RD]; PowerPC::ppcState.spr[index] = PowerPC::ppcState.gpr[inst.RD];
// Our DMA emulation is highly inaccurate - instead of properly emulating the queue // Our DMA emulation is highly inaccurate - instead of properly emulating the queue
// and so on, we simply make all DMA:s complete instantaneously. // and so on, we simply make all DMA:s complete instantaneously.
@ -320,7 +320,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
case SPR_PVR: case SPR_PVR:
// PVR is a read-only register so maintain its value. // PVR is a read-only register so maintain its value.
rSPR(index) = old_value; PowerPC::ppcState.spr[index] = old_value;
break; break;
case SPR_HID0: // HID0 case SPR_HID0: // HID0
@ -352,7 +352,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
// Despite being documented as a read-only register, it actually isn't. Bits // Despite being documented as a read-only register, it actually isn't. Bits
// 0-4 (27-31 from a little endian perspective) are modifiable. The rest are not // 0-4 (27-31 from a little endian perspective) are modifiable. The rest are not
// affected, as those bits are reserved and ignore writes to them. // affected, as those bits are reserved and ignore writes to them.
rSPR(index) &= 0xF8000000; PowerPC::ppcState.spr[index] &= 0xF8000000;
break; break;
case SPR_HID2: case SPR_HID2:
@ -360,22 +360,23 @@ void Interpreter::mtspr(UGeckoInstruction inst)
// TODO: emulate locked cache and DMA bits. // TODO: emulate locked cache and DMA bits.
// Only the lower half of the register (upper half from a little endian perspective) // Only the lower half of the register (upper half from a little endian perspective)
// is modifiable, except for the DMAQL field. // is modifiable, except for the DMAQL field.
rSPR(index) = (rSPR(index) & 0xF0FF0000) | (old_value & 0x0F000000); PowerPC::ppcState.spr[index] =
(PowerPC::ppcState.spr[index] & 0xF0FF0000) | (old_value & 0x0F000000);
break; break;
case SPR_HID4: case SPR_HID4:
if (old_value != rSPR(index)) if (old_value != PowerPC::ppcState.spr[index])
{ {
INFO_LOG_FMT(POWERPC, "HID4 updated {:x} {:x}", old_value, rSPR(index)); INFO_LOG_FMT(POWERPC, "HID4 updated {:x} {:x}", old_value, PowerPC::ppcState.spr[index]);
PowerPC::IBATUpdated(); PowerPC::IBATUpdated();
PowerPC::DBATUpdated(); PowerPC::DBATUpdated();
} }
break; break;
case SPR_WPAR: case SPR_WPAR:
ASSERT_MSG(POWERPC, rSPR(SPR_WPAR) == GPFifo::GATHER_PIPE_PHYSICAL_ADDRESS, ASSERT_MSG(POWERPC, PowerPC::ppcState.spr[SPR_WPAR] == GPFifo::GATHER_PIPE_PHYSICAL_ADDRESS,
"Gather pipe changed to unexpected address {:08x} @ PC {:08x}", rSPR(SPR_WPAR), "Gather pipe changed to unexpected address {:08x} @ PC {:08x}",
PowerPC::ppcState.pc); PowerPC::ppcState.spr[SPR_WPAR], PowerPC::ppcState.pc);
Core::System::GetInstance().GetGPFifo().ResetGatherPipe(); Core::System::GetInstance().GetGPFifo().ResetGatherPipe();
break; break;
@ -428,7 +429,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
break; break;
case SPR_XER: case SPR_XER:
PowerPC::SetXER(UReg_XER{rSPR(index)}); PowerPC::SetXER(UReg_XER{PowerPC::ppcState.spr[index]});
break; break;
case SPR_DBAT0L: case SPR_DBAT0L:
@ -447,9 +448,10 @@ void Interpreter::mtspr(UGeckoInstruction inst)
case SPR_DBAT6U: case SPR_DBAT6U:
case SPR_DBAT7L: case SPR_DBAT7L:
case SPR_DBAT7U: case SPR_DBAT7U:
if (old_value != rSPR(index)) if (old_value != PowerPC::ppcState.spr[index])
{ {
INFO_LOG_FMT(POWERPC, "DBAT updated {} {:x} {:x}", index, old_value, rSPR(index)); INFO_LOG_FMT(POWERPC, "DBAT updated {} {:x} {:x}", index, old_value,
PowerPC::ppcState.spr[index]);
PowerPC::DBATUpdated(); PowerPC::DBATUpdated();
} }
break; break;
@ -470,9 +472,10 @@ void Interpreter::mtspr(UGeckoInstruction inst)
case SPR_IBAT6U: case SPR_IBAT6U:
case SPR_IBAT7L: case SPR_IBAT7L:
case SPR_IBAT7U: case SPR_IBAT7U:
if (old_value != rSPR(index)) if (old_value != PowerPC::ppcState.spr[index])
{ {
INFO_LOG_FMT(POWERPC, "IBAT updated {} {:x} {:x}", index, old_value, rSPR(index)); INFO_LOG_FMT(POWERPC, "IBAT updated {} {:x} {:x}", index, old_value,
PowerPC::ppcState.spr[index]);
PowerPC::IBATUpdated(); PowerPC::IBATUpdated();
} }
break; break;

2
Source/Core/Core/PowerPC/PowerPC.cpp
View File

@ -106,7 +106,7 @@ void DoState(PointerWrap& p)
// and because the values it's changing have been added to CoreTiming::DoState, so it might // and because the values it's changing have been added to CoreTiming::DoState, so it might
// conflict to mess with them here. // conflict to mess with them here.
// rSPR(SPR_DEC) = SystemTimers::GetFakeDecrementer(); // PowerPC::ppcState.spr[SPR_DEC] = SystemTimers::GetFakeDecrementer();
// *((u64 *)&TL) = SystemTimers::GetFakeTimeBase(); //works since we are little endian and TL // *((u64 *)&TL) = SystemTimers::GetFakeTimeBase(); //works since we are little endian and TL
// comes first :) // comes first :)

1
Source/Core/Core/PowerPC/PowerPC.h
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@ -246,7 +246,6 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
#define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2]) #define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2])
#define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3]) #define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3])
#define rSPR(i) PowerPC::ppcState.spr[i]
#define LR PowerPC::ppcState.spr[SPR_LR] #define LR PowerPC::ppcState.spr[SPR_LR]
#define CTR PowerPC::ppcState.spr[SPR_CTR] #define CTR PowerPC::ppcState.spr[SPR_CTR]
#define rDEC PowerPC::ppcState.spr[SPR_DEC] #define rDEC PowerPC::ppcState.spr[SPR_DEC]