fix some recently agitated gxfifo-related asserts
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d55eb9ba06
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f8c453def5
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@ -165,25 +165,16 @@ void GFX_FIFOclear()
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static void GXF_FIFO_handleEvents()
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static void GXF_FIFO_handleEvents()
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{
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{
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if(gxFIFO.size <= 127)
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bool low = gxFIFO.size <= 127;
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{
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bool lowchange = MMU_new.gxstat.fifo_low ^ low;
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//TODO - should this always happen, over and over, until the dma is disabled?
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MMU_new.gxstat.fifo_low = low;
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//or only when we change to this state?
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if(low) triggerDma(EDMAMode_GXFifo);
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if(MMU_new.gxstat.gxfifo_irq == 1)
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setIF(0, (1<<21)); //the half gxfifo irq
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//might need to trigger a gxfifo dma
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bool empty = gxFIFO.size == 0;
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triggerDma(EDMAMode_GXFifo);
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bool emptychange = MMU_new.gxstat.fifo_empty ^ empty;
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}
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MMU_new.gxstat.fifo_empty = empty;
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if(gxFIFO.size == 0) {
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//we just went to empty
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if(MMU_new.gxstat.gxfifo_irq == 2)
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setIF(0, (1<<21)); //the empty gxfifo irq
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}
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if(emptychange||lowchange) NDS_Reschedule();
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}
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}
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void GFX_FIFOsend(u8 cmd, u32 param)
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void GFX_FIFOsend(u8 cmd, u32 param)
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@ -1267,11 +1267,11 @@ u32 MMU_struct::gen_IF()
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case 0: //never
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case 0: //never
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break;
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break;
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case 1: //less than half full
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case 1: //less than half full
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if(gxFIFO.size <= 127)
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if(MMU_new.gxstat.fifo_low)
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IF |= IRQ_MASK_ARM9_GXFIFO;
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IF |= IRQ_MASK_ARM9_GXFIFO;
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break;
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break;
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case 2: //empty
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case 2: //empty
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if(gxFIFO.size == 0)
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if(MMU_new.gxstat.fifo_empty)
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IF |= IRQ_MASK_ARM9_GXFIFO;
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IF |= IRQ_MASK_ARM9_GXFIFO;
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break;
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break;
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case 3: //reserved/unknown
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case 3: //reserved/unknown
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@ -116,6 +116,8 @@ struct TGXSTAT : public TRegister_32
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{
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{
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TGXSTAT() {
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TGXSTAT() {
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gxfifo_irq = se = tr = tb = sb = 0;
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gxfifo_irq = se = tr = tb = sb = 0;
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fifo_empty = true;
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fifo_low = false;
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}
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}
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u8 tb; //test busy
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u8 tb; //test busy
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u8 tr; //test result
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u8 tr; //test result
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@ -123,6 +125,8 @@ struct TGXSTAT : public TRegister_32
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u8 sb; //stack busy
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u8 sb; //stack busy
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u8 gxfifo_irq; //irq configuration
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u8 gxfifo_irq; //irq configuration
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bool fifo_empty, fifo_low;
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virtual u32 read32();
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virtual u32 read32();
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virtual void write32(const u32 val);
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virtual void write32(const u32 val);
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@ -453,6 +453,9 @@ static bool mmu_loadstate(EMUFILE* is, int size)
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MMU.reg_IF_bits[0] &= ~0x00260000;
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MMU.reg_IF_bits[0] &= ~0x00260000;
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MMU.reg_IF_bits[1] &= ~0x00060000;
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MMU.reg_IF_bits[1] &= ~0x00060000;
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MMU_new.gxstat.fifo_low = gxFIFO.size <= 127;
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MMU_new.gxstat.fifo_empty = gxFIFO.size == 0;
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return ok;
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return ok;
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}
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}
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