fix some recently agitated gxfifo-related asserts

This commit is contained in:
zeromus 2010-09-21 19:54:33 +00:00
parent d55eb9ba06
commit f8c453def5
4 changed files with 17 additions and 19 deletions

View File

@ -165,25 +165,16 @@ void GFX_FIFOclear()
static void GXF_FIFO_handleEvents()
{
if(gxFIFO.size <= 127)
{
//TODO - should this always happen, over and over, until the dma is disabled?
//or only when we change to this state?
if(MMU_new.gxstat.gxfifo_irq == 1)
setIF(0, (1<<21)); //the half gxfifo irq
bool low = gxFIFO.size <= 127;
bool lowchange = MMU_new.gxstat.fifo_low ^ low;
MMU_new.gxstat.fifo_low = low;
if(low) triggerDma(EDMAMode_GXFifo);
//might need to trigger a gxfifo dma
triggerDma(EDMAMode_GXFifo);
}
if(gxFIFO.size == 0) {
//we just went to empty
if(MMU_new.gxstat.gxfifo_irq == 2)
setIF(0, (1<<21)); //the empty gxfifo irq
}
bool empty = gxFIFO.size == 0;
bool emptychange = MMU_new.gxstat.fifo_empty ^ empty;
MMU_new.gxstat.fifo_empty = empty;
if(emptychange||lowchange) NDS_Reschedule();
}
void GFX_FIFOsend(u8 cmd, u32 param)

View File

@ -1267,11 +1267,11 @@ u32 MMU_struct::gen_IF()
case 0: //never
break;
case 1: //less than half full
if(gxFIFO.size <= 127)
if(MMU_new.gxstat.fifo_low)
IF |= IRQ_MASK_ARM9_GXFIFO;
break;
case 2: //empty
if(gxFIFO.size == 0)
if(MMU_new.gxstat.fifo_empty)
IF |= IRQ_MASK_ARM9_GXFIFO;
break;
case 3: //reserved/unknown

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@ -116,6 +116,8 @@ struct TGXSTAT : public TRegister_32
{
TGXSTAT() {
gxfifo_irq = se = tr = tb = sb = 0;
fifo_empty = true;
fifo_low = false;
}
u8 tb; //test busy
u8 tr; //test result
@ -123,6 +125,8 @@ struct TGXSTAT : public TRegister_32
u8 sb; //stack busy
u8 gxfifo_irq; //irq configuration
bool fifo_empty, fifo_low;
virtual u32 read32();
virtual void write32(const u32 val);

View File

@ -453,6 +453,9 @@ static bool mmu_loadstate(EMUFILE* is, int size)
MMU.reg_IF_bits[0] &= ~0x00260000;
MMU.reg_IF_bits[1] &= ~0x00060000;
MMU_new.gxstat.fifo_low = gxFIFO.size <= 127;
MMU_new.gxstat.fifo_empty = gxFIFO.size == 0;
return ok;
}