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desmume
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fix more of the same &0xF instead of &0x1F in shift ops problem, this time in arm opcodes.

This commit is contained in:
zeromus 2009-01-14 19:03:15 +00:00
parent 066681fce4
commit f5556d2a16
1 changed files with 4 additions and 4 deletions
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8
desmume/src/arm_instructions.cpp
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@ -187,10 +187,10 @@ extern volatile BOOL execute;
}
#define ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
if((shift_op==0)||((shift_op&0xF)==0))\
if((shift_op==0)||((shift_op&0x1F)==0))\
shift_op=cpu->R[REG_POS(i,0)];\
else\
shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));
shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0x1F));
#define S_ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
u32 c = cpu->CPSR.bits.C;\
@ -198,7 +198,7 @@ extern volatile BOOL execute;
shift_op=cpu->R[REG_POS(i,0)];\
else\
{\
shift_op&=0xF;\
shift_op&=0x1F;\
if(shift_op==0)\
{\
shift_op=cpu->R[REG_POS(i,0)];\
@ -207,7 +207,7 @@ extern volatile BOOL execute;
else\
{\
c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));\
shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0x1F));\
}\
}