parent
f04f80ba20
commit
f41d634d5a
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@ -416,22 +416,7 @@ u8 *MMU_RenderMapToLCD(u32 vram_addr)
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vram_addr &= 0x01FFFFF;
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u8 engine_offset = (vram_addr >> 14);
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u8 block = MMU.VRAM_MAP[engine][engine_offset];
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if (block == 7)
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{
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switch (engine)
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{
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case 0: // Engine ABG
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return (ARM9Mem.ARM9_ABG + vram_addr);
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case 1: // Engine BBG
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return (ARM9Mem.ARM9_BBG + vram_addr);
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case 2: // Engine AOBJ
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return (ARM9Mem.ARM9_AOBJ + vram_addr);
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case 3: // Engine BOBJ
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return (ARM9Mem.ARM9_BOBJ + vram_addr);
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}
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LOG("render: VRAM not mapped to LCD\n");
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return NULL;
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}
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if (block == 7) return (EngineAddr[engine] + vram_addr);
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vram_addr -= MMU.LCD_VRAM_ADDR[block];
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return (LCDdst[block] + vram_addr);
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}
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@ -462,6 +447,13 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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{
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if (!(VRAMBankCnt & 0x80)) return;
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if (!(VRAMBankCnt & 0x07)) return;
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for (int i = 0; i < 4; i++)
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{
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for (int t = 0; t < 32; t++)
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if (MMU.VRAM_MAP[i][t] == block)
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MMU.VRAM_MAP[i][t] = 7;
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}
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u32 vram_map_addr = 0xFFFFFFFF;
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u8 *LCD_addr = LCDdst[block];
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@ -586,13 +578,6 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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break;
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}
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for (int i = 0; i < 4; i++)
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{
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for (int t = 0; t < 32; t++)
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if (MMU.VRAM_MAP[i][t] == block)
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MMU.VRAM_MAP[i][t] = 7;
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}
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if (vram_map_addr != 0xFFFFFFFF)
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{
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u8 engine = (vram_map_addr >> 21);
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