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core-add ldrex and strex instructions to arm

This commit is contained in:
zeromus 2012-03-20 01:18:01 +00:00
parent afc0eef0b7
commit f18e4a4df2
3 changed files with 4122 additions and 4096 deletions
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10
desmume/src/Disassembler.cpp
View File

@ -2133,6 +2133,11 @@ static char * OP_LDR_M_IMM_OFF(u32 adr, u32 i, char * txt)
sprintf(txt, "LDR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0x7FF)); sprintf(txt, "LDR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0x7FF));
return txt;} return txt;}
static char * OP_LDREX(u32 adr, u32 i, char * txt)
{
sprintf(txt, "LDREX%s %s, [%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)]);
return txt;}
static char * OP_LDR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) static char * OP_LDR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt)
{ {
LDRSTR_LSL_IMM(LDR, "", "", "]"); LDRSTR_LSL_IMM(LDR, "", "", "]");
@ -2442,6 +2447,11 @@ static char * OP_STR_M_IMM_OFF(u32 adr, u32 i, char * txt)
sprintf(txt, "STR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0x7FF)); sprintf(txt, "STR%s %s, [%s, -#%X]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,16)], (int)(i&0x7FF));
return txt;} return txt;}
static char * OP_STREX(u32 adr, u32 i, char * txt)
{
sprintf(txt, "STREX%s %s, %s, [%s]", Condition[CONDITION(i)], Registre[REG_POS(i,12)], Registre[REG_POS(i,0)], Registre[REG_POS(i,16)]);
return txt;}
static char * OP_STR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt) static char * OP_STR_P_LSL_IMM_OFF(u32 adr, u32 i, char * txt)
{ {
LDRSTR_LSL_IMM(STR, "", "", "]"); LDRSTR_LSL_IMM(STR, "", "", "]");

16
desmume/src/arm_instructions.cpp
View File

@ -3726,6 +3726,13 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF(const u32 i)
OP_LDR(3, 5); OP_LDR(3, 5);
} }
TEMPLATE static u32 FASTCALL OP_LDREX(const u32 i)
{
u32 adr = cpu->R[REG_POS(i,16)];
cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3));
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3,adr);
}
TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(const u32 i)
{ {
LSL_IMM; LSL_IMM;
@ -4216,6 +4223,15 @@ TEMPLATE static u32 FASTCALL OP_STR_M_IMM_OFF(const u32 i)
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr); return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
} }
TEMPLATE static u32 FASTCALL OP_STREX(const u32 i)
{
u32 adr = cpu->R[REG_POS(i,16)];
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]);
cpu->R[REG_POS(i,12)] = 0;
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
}
TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i) TEMPLATE static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(const u32 i)
{ {
LSL_IMM; LSL_IMM;

4
desmume/src/instruction_tabdef.inc
View File

@ -413,7 +413,7 @@
/* 0001 1000 0110 */ TABDECL( OP_ORR_ROR_IMM), /* 0001 1000 0110 */ TABDECL( OP_ORR_ROR_IMM),
/* 0001 1000 0111 */ TABDECL( OP_ORR_ROR_REG), /* 0001 1000 0111 */ TABDECL( OP_ORR_ROR_REG),
/* 0001 1000 1000 */ TABDECL( OP_ORR_LSL_IMM), /* 0001 1000 1000 */ TABDECL( OP_ORR_LSL_IMM),
/* 0001 1000 1001 */ TABDECL( OP_UND), /* 0001 1000 1001 */ TABDECL( OP_STREX),
/* 0001 1000 1010 */ TABDECL( OP_ORR_LSR_IMM), // OOO 110O O 1010 /* 0001 1000 1010 */ TABDECL( OP_ORR_LSR_IMM), // OOO 110O O 1010
/* 0001 1000 1011 */ TABDECL( OP_STRH_P_REG_OFF), /* 0001 1000 1011 */ TABDECL( OP_STRH_P_REG_OFF),
/* 0001 1000 1100 */ TABDECL( OP_ORR_ASR_IMM), /* 0001 1000 1100 */ TABDECL( OP_ORR_ASR_IMM),
@ -429,7 +429,7 @@
/* 0001 1001 0110 */ TABDECL( OP_ORR_S_ROR_IMM), /* 0001 1001 0110 */ TABDECL( OP_ORR_S_ROR_IMM),
/* 0001 1001 0111 */ TABDECL( OP_ORR_S_ROR_REG), /* 0001 1001 0111 */ TABDECL( OP_ORR_S_ROR_REG),
/* 0001 1001 1000 */ TABDECL( OP_ORR_S_LSL_IMM), /* 0001 1001 1000 */ TABDECL( OP_ORR_S_LSL_IMM),
/* 0001 1001 1001 */ TABDECL( OP_UND), /* 0001 1001 1001 */ TABDECL( OP_LDREX),
/* 0001 1001 1010 */ TABDECL( OP_ORR_S_LSR_IMM), /* 0001 1001 1010 */ TABDECL( OP_ORR_S_LSR_IMM),
/* 0001 1001 1011 */ TABDECL( OP_LDRH_P_REG_OFF), /* 0001 1001 1011 */ TABDECL( OP_LDRH_P_REG_OFF),
/* 0001 1001 1100 */ TABDECL( OP_ORR_S_ASR_IMM), /* 0001 1001 1100 */ TABDECL( OP_ORR_S_ASR_IMM),