core:
- fix VRAM mapping control (now this correct, in future need only add WRAM mapping);
This commit is contained in:
mtabachenko
parent
626e94e493
commit
f04f80ba20
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@ -52,6 +52,8 @@ static const int save_types[7][2] = {
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#define ROM_MASK 3
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//#define CHECK_VRAM
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//#define _MMU_DEBUG
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#ifdef _MMU_DEBUG
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@ -234,8 +236,8 @@ TWaitState MMU_struct::MMU_WAIT32[2][16] = {
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u32 gxIRQ = 0;
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// VRAM mapping
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static u8 last_engine_offset[4] = {0x00, 0x00, 0x00, 0x00};
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u8 *LCDdst[10] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
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u8 *EngineAddr[4] = { NULL, NULL, NULL, NULL };
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const static u32 LCDdata[10][2]= {
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{0x6800000, 8}, // Bank A
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{0x6820000, 8}, // Bank B
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@ -305,10 +307,10 @@ u32 DMADst[2][4] = {{0, 0, 0, 0}, {0, 0, 0, 0}};
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void MMU_clearMem()
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{
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memset(ARM9Mem.ARM9_ABG, 0, 0x080000); // TODO: remove this
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memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000); // don't need now
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memset(ARM9Mem.ARM9_BBG, 0, 0x020000); //
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memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000); // ----------------|
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memset(ARM9Mem.ARM9_ABG, 0, 0x080000);
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memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000);
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memset(ARM9Mem.ARM9_BBG, 0, 0x020000);
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memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000);
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memset(ARM9Mem.ARM9_DTCM, 0, 0x4000);
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memset(ARM9Mem.ARM9_ITCM, 0, 0x8000);
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@ -375,6 +377,11 @@ void MMU_clearMem()
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LCDdst[8] = ARM9Mem.ARM9_LCD + 0x98000; // Bank H
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LCDdst[9] = ARM9Mem.ARM9_LCD + 0xA0000; // Bank I
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EngineAddr[0] = ARM9Mem.ARM9_ABG; // Engine ABG
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EngineAddr[1] = ARM9Mem.ARM9_BBG; // Engine BBG
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EngineAddr[2] = ARM9Mem.ARM9_AOBJ; // Engine BOBJ
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EngineAddr[3] = ARM9Mem.ARM9_BOBJ; // Engine BOBJ
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for (int i = 0; i < 4; i++)
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{
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ARM9Mem.ExtPal[0][i] = ARM9Mem.ARM9_LCD;
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@ -408,9 +415,23 @@ u8 *MMU_RenderMapToLCD(u32 vram_addr)
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u8 engine = (vram_addr >> 21);
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vram_addr &= 0x01FFFFF;
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u8 engine_offset = (vram_addr >> 14);
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if (engine_offset > 31) return NULL;
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u8 block = MMU.VRAM_MAP[engine][engine_offset];
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if (block == 7) return NULL;
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if (block == 7)
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{
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switch (engine)
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{
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case 0: // Engine ABG
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return (ARM9Mem.ARM9_ABG + vram_addr);
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case 1: // Engine BBG
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return (ARM9Mem.ARM9_BBG + vram_addr);
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case 2: // Engine AOBJ
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return (ARM9Mem.ARM9_AOBJ + vram_addr);
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case 3: // Engine BOBJ
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return (ARM9Mem.ARM9_BOBJ + vram_addr);
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}
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LOG("render: VRAM not mapped to LCD\n");
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return NULL;
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}
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vram_addr -= MMU.LCD_VRAM_ADDR[block];
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return (LCDdst[block] + vram_addr);
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}
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@ -430,36 +451,9 @@ static FORCEINLINE u32 MMU_LCDmap(u8 proc, u32 addr)
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addr &= 0x01FFFFF;
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u8 engine_offset = (addr >> 14);
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u8 block = MMU.VRAM_MAP[engine][engine_offset];
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if (block == 7) // corrections VRAM mapping
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{
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block = MMU.VRAM_MAP[engine][last_engine_offset[engine]];
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//LOG("Engine offset = %i/%i in block %i (size %i, offs %i): \n",
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//engine_offset, last_engine_offset[engine], block,
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//LCDdata[block][1], engine_offset+LCDdata[block][1]);
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for (int i = 0; i < LCDdata[block][1]; i++)
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{
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if (MMU.VRAM_MAP[engine][engine_offset + i] != 7)
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LOG("\nVRAM already mapping %i\n", i);
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MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
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}
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}
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//LOG("VRAM %i: engine=%i (offset=%i), map address = 0x%X, MMU address = 0x%X\n", block, engine, engine_offset, vram_addr, *addr);
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last_engine_offset[engine] = engine_offset;
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//u32 tmp02 = addr;
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if (block == 7) return save_addr; // not mapped to LCD
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addr -= MMU.LCD_VRAM_ADDR[block];
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addr += LCDdata[block][0];
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#if 0
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if ((addr < 0x6800000) || (addr> 0x68A3FFF)) // FIXME: this is hack
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{
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LOG("Address is out range 0x%X in block %i\n", addr, block);
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addr = save_addr;
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}
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#endif
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}
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return (addr);
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}
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@ -588,7 +582,6 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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{
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ARM9Mem.ObjExtPal[0][0] = LCD_addr;
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ARM9Mem.ObjExtPal[0][1] = LCD_addr + 0x2000;
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}
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break;
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}
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@ -608,12 +601,14 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
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MMU.LCDCenable[block] = TRUE;
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for (unsigned int i = 0; i < LCDdata[block][1]; i++)
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for (unsigned int i = 0; i <= LCDdata[block][1]; i++)
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MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
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//INFO("VRAM %i mapping: engine=%i (offset=%i), address = 0x%X, MST=%i\n", block, engine, engine_offset, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
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//LOG("VRAM %i mapping: engine=%i (offset=%i, size=%i), address = 0x%X, MST=%i\n",
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// block, engine, engine_offset, LCDdata[block][1]*0x4000, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
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return;
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}
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MMU.LCDCenable[block] = FALSE;
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}
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@ -1090,8 +1085,19 @@ void FASTCALL _MMU_write8(u32 adr, u8 val)
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if(proc == ARMCPU_ARM9) GPU_setBLDY_EVY(SubScreen.gpu,val) ;
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break;
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#ifdef CHECKVRAM
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case 0x4000247: // block 7
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INFO("------- MMU write 08: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
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T1ReadByte(MMU.MMU_MEM[proc][0x40], 0x241));
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break;
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#endif
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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#ifdef CHECKVRAM
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if(proc == ARMCPU_ARM7)
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INFO("******* MMU write 08: writing in VRAM block B 0x%X (stat=0x%X)\n", val,
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T1ReadByte(MMU.MMU_MEM[proc][0x40], 0x241));
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#endif
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case REG_VRAMCNTC:
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case REG_VRAMCNTD:
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case REG_VRAMCNTE:
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@ -1537,6 +1543,22 @@ void FASTCALL _MMU_write16(u32 adr, u16 val)
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}
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return;
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}
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#ifdef CHECKVRAM
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case 0x4000247: // block 7
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INFO("-------- MMU write 16: writing in VRAM block 7 0x%X\n", val);
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break;
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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case REG_VRAMCNTC:
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case REG_VRAMCNTD:
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case REG_VRAMCNTE:
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case REG_VRAMCNTF:
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case REG_VRAMCNTG:
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case REG_VRAMCNTH:
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case REG_VRAMCNTI:
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INFO("MMU write 16: VRAM block %i 0x%X\n", adr-REG_VRAMCNTA, val);
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break;
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#else
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case REG_VRAMCNTA:
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MMU_write8(proc,adr,val & 0xFF) ;
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@ -1557,7 +1579,7 @@ void FASTCALL _MMU_write16(u32 adr, u16 val)
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case REG_VRAMCNTI:
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MMU_write8(proc,adr,val & 0xFF) ;
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return ;
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#endif
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case REG_IE :
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MMU.reg_IE[proc] = (MMU.reg_IE[proc]&0xFFFF0000) | val;
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if ( MMU.reg_IME[proc]) {
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@ -2374,6 +2396,23 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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//GPULOG("SUB INIT 32B %08X\r\n", val);
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x1000, val);
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return;
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#ifdef CHECKVRAM
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case 0x4000247: // block 7
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INFO("------- MMU write 32: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
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T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x241));
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break;
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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case REG_VRAMCNTC:
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case REG_VRAMCNTD:
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case REG_VRAMCNTE:
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case REG_VRAMCNTF:
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case REG_VRAMCNTG:
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case REG_VRAMCNTH:
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case REG_VRAMCNTI:
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INFO("MMU write 32: VRAM block %i 0x%X\n", adr-REG_VRAMCNTA, val);
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break;
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#else
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case REG_VRAMCNTA:
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case REG_VRAMCNTE:
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MMU_write8(proc,adr,val & 0xFF) ;
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@ -2384,6 +2423,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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case REG_VRAMCNTI:
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MMU_write8(proc,adr,val & 0xFF) ;
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return ;
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#endif
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case REG_IME : {
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u32 old_val = MMU.reg_IME[proc];
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