fixed write to window registers
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defa6952f8
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@ -214,6 +214,11 @@ typedef union windowcnt_t
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/*13*/ unsigned WIN1_Effect_Enable:1;
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/*14*/ unsigned :2;
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} bitfield ;
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struct
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{
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unsigned char low ;
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unsigned char high ;
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} bytes ;
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unsigned short val ;
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} windowcnt_t ;
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@ -528,7 +533,9 @@ void GPU_setWINDOW_XDIM_Component(GPU *gpu, u8 v, u8 num) ;
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void GPU_setWINDOW_YDIM_Component(GPU *gpu, u8 v, u8 num) ;
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void GPU_setWINDOW_INCNT(GPU *gpu, u16 v) ;
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void GPU_setWINDOW_INCNT(GPU *gpu, u16 v) ;
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void GPU_setWINDOW_OUTCNT(GPU *gpu, u16 v) ;
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void GPU_setWINDOW_INCNT_Component(GPU *gpu, u8 v,u8 num) ;
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void GPU_setWINDOW_OUTCNT_Component(GPU *gpu, u8 v,u8 num) ;
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void GPU_setMASTER_BRIGHT (GPU *gpu, u16 v);
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@ -803,6 +803,30 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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case REG_DISPB_WIN1V+1:
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GPU_setWINDOW_YDIM_Component(SubScreen.gpu,val,3) ;
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break ;
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case REG_DISPA_WININ:
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GPU_setWINDOW_INCNT_Component(MainScreen.gpu,val,0) ;
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break ;
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case REG_DISPA_WININ+1:
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GPU_setWINDOW_INCNT_Component(MainScreen.gpu,val,1) ;
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break ;
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case REG_DISPA_WINOUT:
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GPU_setWINDOW_OUTCNT_Component(MainScreen.gpu,val,0) ;
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break ;
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case REG_DISPA_WINOUT+1:
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GPU_setWINDOW_OUTCNT_Component(MainScreen.gpu,val,1) ;
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break ;
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case REG_DISPB_WININ:
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GPU_setWINDOW_INCNT_Component(SubScreen.gpu,val,0) ;
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break ;
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case REG_DISPB_WININ+1:
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GPU_setWINDOW_INCNT_Component(SubScreen.gpu,val,1) ;
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break ;
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case REG_DISPB_WINOUT:
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GPU_setWINDOW_OUTCNT_Component(SubScreen.gpu,val,0) ;
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break ;
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case REG_DISPB_WINOUT+1:
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GPU_setWINDOW_OUTCNT_Component(SubScreen.gpu,val,1) ;
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break ;
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#ifdef LOG_CARD
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case 0x040001A0 : /* TODO (clear): ??? */
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case 0x040001A1 :
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@ -1244,6 +1268,18 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
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case REG_DISPB_MASTERBRIGHT:
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GPU_setMASTER_BRIGHT (SubScreen.gpu, val);
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break;
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case REG_DISPA_WININ:
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GPU_setWINDOW_INCNT(MainScreen.gpu, val) ;
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break ;
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case REG_DISPA_WINOUT:
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GPU_setWINDOW_OUTCNT(MainScreen.gpu, val) ;
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break ;
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case REG_DISPB_WININ:
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GPU_setWINDOW_INCNT(SubScreen.gpu, val) ;
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break ;
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case REG_DISPB_WINOUT:
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GPU_setWINDOW_OUTCNT(SubScreen.gpu, val) ;
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break ;
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case REG_IME :
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MMU.reg_IME[proc] = val&1;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x208, val);
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@ -1746,6 +1782,14 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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//GPULOG("SUB INIT 32B %08X\r\n", val);
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x1000, val);
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return;
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case REG_DISPA_WININ:
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GPU_setWINDOW_INCNT(MainScreen.gpu, val & 0xFFFF) ;
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GPU_setWINDOW_OUTCNT(MainScreen.gpu, (val >> 16) & 0xFFFF) ;
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break ;
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case REG_DISPB_WININ:
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GPU_setWINDOW_INCNT(SubScreen.gpu, val & 0xFFFF) ;
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GPU_setWINDOW_OUTCNT(SubScreen.gpu, (val >> 16) & 0xFFFF) ;
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break ;
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case REG_IME :
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MMU.reg_IME[proc] = val & 1;
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