- fix CPSR flags in ADC/SBC :P
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01ef774e13
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e2dfe00574
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@ -449,8 +449,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i)
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.C = CarryFrom(Rd, Rm + cpu->CPSR.bits.C);
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cpu->CPSR.bits.C = CarryFrom(Rd + cpu->CPSR.bits.C, Rm + cpu->CPSR.bits.C);
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cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 0)], Rd, Rm + cpu->CPSR.bits.C);
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cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 0)], Rd + cpu->CPSR.bits.C, Rm + cpu->CPSR.bits.C);
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return 1;
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return 1;
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}
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}
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@ -469,8 +469,8 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i)
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.C = !CarryFrom(Rd, Rm - !cpu->CPSR.bits.C);
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cpu->CPSR.bits.C = !CarryFrom(Rd - !cpu->CPSR.bits.C, Rm - !cpu->CPSR.bits.C);
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cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 0)], Rd, Rm - !cpu->CPSR.bits.C);
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cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 0)], Rd - !cpu->CPSR.bits.C, Rm - !cpu->CPSR.bits.C);
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return 1;
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return 1;
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}
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}
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