Conversion from ARM_CPU (c++) to C ! :)
This commit is contained in:
thoduv
parent
97d25810fd
commit
dcf1e19871
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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This file is part of DeSmuME
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DeSmuME is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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DeSmuME is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with DeSmuME; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "ARM_CPU.hpp"
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#include "arm_instructions.hpp"
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#include "thumb_instructions.hpp"
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#include "MMU.hpp"
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#include "CP15.hpp"
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#include "bios.hpp"
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#include <stdlib.h>
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#define SWAP(a, b, c) c=a;\
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a=b;\
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b=c;
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armcpu_t *armcpu_new(unsigned long id)
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{
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armcpu_t *armcpu;
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armcpu = (armcpu_t*)malloc(sizeof(armcpu_t));
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if(!armcpu) return NULL;
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armcpu->proc_ID = id;
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if(id==0) armcpu->swi_tab = ARM9_swi_tab;
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else armcpu->swi_tab = ARM7_swi_tab;
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armcpu_init(armcpu, 0);
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return armcpu;
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}
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void armcpu_init(armcpu_t *armcpu, unsigned long adr)
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{
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armcpu->LDTBit = (armcpu->proc_ID==0); //Si ARM9 utiliser le syte v5 pour le load
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armcpu->intVector = 0xFFFF0000 * (armcpu->proc_ID==0);
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armcpu->waitIRQ = false;
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armcpu->wirq = false;
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if(armcpu->coproc[15]) delete armcpu->coproc[15];
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for(unsigned long i = 0; i < 15; ++i)
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{
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armcpu->R[i] = 0;
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armcpu->coproc[i] = NULL;
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}
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armcpu->CPSR.val = armcpu->SPSR.val = SYS;
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armcpu->R13_usr = armcpu->R14_usr = 0;
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armcpu->R13_svc = armcpu->R14_svc = 0;
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armcpu->R13_abt = armcpu->R14_abt = 0;
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armcpu->R13_und = armcpu->R14_und = 0;
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armcpu->R13_irq = armcpu->R14_irq = 0;
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armcpu->R8_fiq = armcpu->R9_fiq = armcpu->R10_fiq = armcpu->R11_fiq = armcpu->R12_fiq = armcpu->R13_fiq = armcpu->R14_fiq = 0;
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armcpu->SPSR_svc.val = armcpu->SPSR_abt.val = armcpu->SPSR_und.val = armcpu->SPSR_irq.val = armcpu->SPSR_fiq.val = 0;
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armcpu->next_instruction = adr;
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armcpu->R[15] = adr;
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armcpu->coproc[15] = new CP15(armcpu);
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armcpu_prefetch(armcpu);
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}
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unsigned long armcpu_switchMode(armcpu_t *armcpu, unsigned char mode)
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{
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unsigned long oldmode = armcpu->CPSR.bits.mode;
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switch(oldmode)
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{
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case USR :
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case SYS :
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armcpu->R13_usr = armcpu->R[13];
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armcpu->R14_usr = armcpu->R[14];
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break;
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case FIQ :
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{
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unsigned long tmp;
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SWAP(armcpu->R[8], armcpu->R8_fiq, tmp);
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SWAP(armcpu->R[9], armcpu->R9_fiq, tmp);
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SWAP(armcpu->R[10], armcpu->R10_fiq, tmp);
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SWAP(armcpu->R[11], armcpu->R11_fiq, tmp);
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SWAP(armcpu->R[12], armcpu->R12_fiq, tmp);
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armcpu->R13_fiq = armcpu->R[13];
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armcpu->R14_fiq = armcpu->R[14];
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armcpu->SPSR_fiq = armcpu->SPSR;
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break;
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}
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case IRQ :
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armcpu->R13_irq = armcpu->R[13];
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armcpu->R14_irq = armcpu->R[14];
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armcpu->SPSR_irq = armcpu->SPSR;
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break;
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case SVC :
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armcpu->R13_svc = armcpu->R[13];
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armcpu->R14_svc = armcpu->R[14];
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armcpu->SPSR_svc = armcpu->SPSR;
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break;
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case ABT :
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armcpu->R13_abt = armcpu->R[13];
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armcpu->R14_abt = armcpu->R[14];
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armcpu->SPSR_abt = armcpu->SPSR;
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break;
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case UND :
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armcpu->R13_und = armcpu->R[13];
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armcpu->R14_und = armcpu->R[14];
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armcpu->SPSR_und = armcpu->SPSR;
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break;
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default :
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break;
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}
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switch(mode)
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{
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case USR :
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case SYS :
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armcpu->R[13] = armcpu->R13_usr;
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armcpu->R[14] = armcpu->R14_usr;
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//SPSR = CPSR;
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break;
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case FIQ :
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{
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unsigned long tmp;
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SWAP(armcpu->R[8], armcpu->R8_fiq, tmp);
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SWAP(armcpu->R[9], armcpu->R9_fiq, tmp);
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SWAP(armcpu->R[10], armcpu->R10_fiq, tmp);
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SWAP(armcpu->R[11], armcpu->R11_fiq, tmp);
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SWAP(armcpu->R[12], armcpu->R12_fiq, tmp);
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armcpu->R[13] = armcpu->R13_fiq;
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armcpu->R[14] = armcpu->R14_fiq;
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armcpu->SPSR = armcpu->SPSR_fiq;
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break;
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}
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case IRQ :
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armcpu->R[13] = armcpu->R13_irq;
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armcpu->R[14] = armcpu->R14_irq;
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armcpu->SPSR = armcpu->SPSR_irq;
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break;
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case SVC :
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armcpu->R[13] = armcpu->R13_svc;
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armcpu->R[14] = armcpu->R14_svc;
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armcpu->SPSR = armcpu->SPSR_svc;
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break;
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case ABT :
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armcpu->R[13] = armcpu->R13_abt;
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armcpu->R[14] = armcpu->R14_abt;
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armcpu->SPSR = armcpu->SPSR_abt;
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break;
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case UND :
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armcpu->R[13] = armcpu->R13_und;
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armcpu->R[14] = armcpu->R14_und;
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armcpu->SPSR = armcpu->SPSR_und;
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break;
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default :
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break;
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}
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armcpu->CPSR.bits.mode = mode & 0x1F;
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return oldmode;
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}
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@ -0,0 +1,257 @@
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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This file is part of DeSmuME
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DeSmuME is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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DeSmuME is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with DeSmuME; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef ARM_CPU
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#define ARM_CPU
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#include "types.h"
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#include "ICoProc.hpp"
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#include "arm_instructions.hpp"
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#include "thumb_instructions.hpp"
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#include "MMU.hpp"
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#include "CP15.hpp"
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#include "bios.hpp"
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#define BIT_N(i,n) (((i)>>(n))&1)
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#define CONDITION(i) (i)>>28
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#define CODE(i) (((i)>>25)&0X7)
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#define OPCODE(i) (((i)>>21)&0xF)
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#define SIGNEBIT(i) BIT_N(i,20)
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#define BIT0(i) ((i)&1)
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#define BIT1(i) BIT_N(i,1)
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#define BIT2(i) BIT_N(i,2)
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#define BIT3(i) BIT_N(i,3)
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#define BIT4(i) BIT_N(i,4)
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#define BIT5(i) BIT_N(i,5)
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#define BIT6(i) BIT_N(i,6)
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#define BIT7(i) BIT_N(i,7)
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#define BIT8(i) BIT_N(i,8)
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#define BIT9(i) BIT_N(i,9)
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#define BIT10(i) BIT_N(i,10)
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#define BIT11(i) BIT_N(i,11)
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#define BIT12(i) BIT_N(i,12)
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#define BIT13(i) BIT_N(i,13)
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#define BIT14(i) BIT_N(i,14)
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#define BIT15(i) BIT_N(i,15)
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#define BIT16(i) BIT_N(i,16)
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#define BIT17(i) BIT_N(i,17)
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#define BIT18(i) BIT_N(i,18)
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#define BIT19(i) BIT_N(i,19)
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#define BIT20(i) BIT_N(i,20)
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#define BIT21(i) BIT_N(i,21)
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#define BIT22(i) BIT_N(i,22)
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#define BIT23(i) BIT_N(i,23)
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#define BIT24(i) BIT_N(i,24)
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#define BIT25(i) BIT_N(i,25)
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#define BIT26(i) BIT_N(i,26)
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#define BIT27(i) BIT_N(i,27)
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#define BIT28(i) BIT_N(i,28)
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#define BIT29(i) BIT_N(i,29)
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#define BIT30(i) BIT_N(i,30)
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#define BIT31(i) ((i)>>31)
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#define INSTRUCTION_INDEX(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF))
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#define REG_POS(i,n) (((i)>>n)&0xF)
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#define ROR(i, j) ((((unsigned long)(i))>>(j)) | (((unsigned long)(i))<<(32-(j))))
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#define UNSIGNED_OVERFLOW(a,b,c) ((BIT31(a)&BIT31(b)) | \
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((BIT31(a)|BIT31(b))&BIT31(~c)))
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#define UNSIGNED_UNDERFLOW(a,b,c) ((BIT31(~a)&BIT31(b)) | \
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((BIT31(~a)|BIT31(b))&BIT31(c)))
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#define SIGNED_OVERFLOW(a,b,c) ((BIT31(a)&BIT31(b)&BIT31(~c))|\
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(BIT31(~a)&BIT31(~(b))&BIT31(c)))
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#define SIGNED_UNDERFLOW(a,b,c) ((BIT31(a)&BIT31(~(b))&BIT31(~c))|\
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(BIT31(~a)&BIT31(b)&BIT31(c)))
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#define EQ 0x0
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#define NE 0x1
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#define CS 0x2
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#define CC 0x3
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#define MI 0x4
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#define PL 0x5
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#define VS 0x6
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#define VC 0x7
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#define HI 0x8
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#define LS 0x9
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#define GE 0xA
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#define LT 0xB
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#define GT 0xC
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#define LE 0xD
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#define AL 0xE
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#define TEST_COND(cond, CPSR) (((cond)==AL) ||\
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(((cond)==EQ) && ( CPSR.bits.Z))||\
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(((cond)==NE) && (!CPSR.bits.Z))||\
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(((cond)==CS) && ( CPSR.bits.C))||\
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(((cond)==CC) && (!CPSR.bits.C))||\
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(((cond)==MI) && ( CPSR.bits.N))||\
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(((cond)==PL) && (!CPSR.bits.N))||\
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(((cond)==VS) && ( CPSR.bits.V))||\
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(((cond)==VC) && (!CPSR.bits.V))||\
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(((cond)==HI) && (CPSR.bits.C) && (!CPSR.bits.Z))||\
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(((cond)==LS) && ((CPSR.bits.Z) || (!CPSR.bits.C)))||\
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(((cond)==GE) && (CPSR.bits.N==CPSR.bits.V))||\
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(((cond)==LT) && (CPSR.bits.N!=CPSR.bits.V))||\
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(((cond)==GT) && (CPSR.bits.Z==0) && (CPSR.bits.N==CPSR.bits.V))||\
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(((cond)==LE) && ((CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V))))
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enum Mode
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{
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USR = 0x10,
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FIQ = 0x11,
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IRQ = 0x12,
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SVC = 0x13,
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ABT = 0x17,
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UND = 0x1B,
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SYS = 0x1F
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};
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extern bool execute;
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union Status_Reg
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{
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struct
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{
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unsigned long mode : 5,
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T : 1,
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F : 1,
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I : 1,
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RAZ : 19,
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Q : 1,
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V : 1,
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C : 1,
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Z : 1,
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N : 1;
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} bits;
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unsigned long val;
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};
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typedef struct
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{
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unsigned long proc_ID;
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unsigned long instruction; //4
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unsigned long instruct_adr; //8
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unsigned long next_instruction; //12
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unsigned long R[16]; //16
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Status_Reg CPSR; //80
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Status_Reg SPSR;
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unsigned long R13_usr, R14_usr;
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unsigned long R13_svc, R14_svc;
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unsigned long R13_abt, R14_abt;
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unsigned long R13_und, R14_und;
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unsigned long R13_irq, R14_irq;
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unsigned long R8_fiq, R9_fiq, R10_fiq, R11_fiq, R12_fiq, R13_fiq, R14_fiq;
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Status_Reg SPSR_svc, SPSR_abt, SPSR_und, SPSR_irq, SPSR_fiq;
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ICoProc * coproc[16];
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unsigned long intVector;
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unsigned char LDTBit; //1 : ARMv5 style 0 : non ARMv5
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bool waitIRQ;
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bool wIRQ;
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bool wirq;
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unsigned long (* *swi_tab)(ARMCPU * cpu);
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} armcpu_t;
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void armcpu_init(armcpu_t *armcpu, unsigned long adr);
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unsigned long armcpu_switchMode(armcpu_t *armcpu, unsigned char mode);
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inline unsigned long armcpu_prefetch(armcpu_t *armcpu)
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{
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if(armcpu->CPSR.bits.T == 0)
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{
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armcpu->instruction = MMU::readWord(armcpu->proc_ID, armcpu->next_instruction);
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armcpu->instruct_adr = armcpu->next_instruction;
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armcpu->next_instruction += 4;
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armcpu->R[15] = armcpu->next_instruction + 4;
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return MMU::MMU_WAIT32[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF];
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}
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armcpu->instruction = MMU::readHWord(armcpu->proc_ID, armcpu->next_instruction);
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armcpu->instruct_adr = armcpu->next_instruction;
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armcpu->next_instruction = armcpu->next_instruction + 2;
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armcpu->R[15] = armcpu->next_instruction + 2;
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return MMU::MMU_WAIT16[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF];
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}
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inline unsigned long armcpu_exec(armcpu_t *armcpu)
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{
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unsigned long c = 1;
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if(armcpu->CPSR.bits.T == 0)
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{
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if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))
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{
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c = arm_instructions_set[INSTRUCTION_INDEX(armcpu->instruction)](armcpu);
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}
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c += armcpu_prefetch(armcpu);
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return c;
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}
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c = thumb_instructions_set[armcpu->instruction>>6](armcpu);
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c += armcpu_prefetch(armcpu);
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return c;
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}
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inline bool irqExeption(armcpu_t *armcpu)
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{
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if(armcpu->CPSR.bits.I) return false;
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Status_Reg tmp = armcpu->CPSR;
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armcpu_switchMode(armcpu, IRQ);
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armcpu->R[14] = armcpu->instruct_adr + 4;
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armcpu->SPSR = tmp;
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armcpu->CPSR.bits.T = 0;
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armcpu->CPSR.bits.I = 1;
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armcpu->next_instruction = armcpu->intVector + 0x18;
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armcpu->R[15] = armcpu->next_instruction;
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armcpu->waitIRQ = 0;
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armcpu_prefetch(armcpu);
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return true;
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}
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inline bool prefetchExeption(armcpu_t *armcpu)
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{
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if(armcpu->CPSR.bits.I) return false;
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Status_Reg tmp = armcpu->CPSR;
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armcpu_switchMode(armcpu, ABT);
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armcpu->R[14] = armcpu->instruct_adr + 4;
|
||||
armcpu->SPSR = tmp;
|
||||
armcpu->CPSR.bits.T = 0;
|
||||
armcpu->CPSR.bits.I = 1;
|
||||
armcpu->next_instruction = armcpu->intVector + 0xC;
|
||||
armcpu->R[15] = armcpu->next_instruction;
|
||||
armcpu->waitIRQ = 0;
|
||||
armcpu_prefetch(armcpu);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue