core:
- temporary implementations for clearing VRAM (garbage on screen);
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@ -227,6 +227,8 @@ u32 MMU_ARM7_WAIT32[16]={
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1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1,
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};
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static u8 MMU_VRAMcntSaved[10];
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void MMU_Init(void) {
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int i;
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@ -256,6 +258,8 @@ void MMU_Init(void) {
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MMU.MMU_WAIT32[0] = MMU_ARM9_WAIT32;
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MMU.MMU_WAIT32[1] = MMU_ARM7_WAIT32;
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memset(MMU_VRAMcntSaved, 0, sizeof(MMU_VRAMcntSaved[0])*10);
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FIFOclear(&MMU.fifos[0]);
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FIFOclear(&MMU.fifos[1]);
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@ -312,6 +316,8 @@ void MMU_clearMem()
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memset(MMU.ARM7_ERAM, 0, 0x010000);
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memset(MMU.ARM7_REG, 0, 0x010000);
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memset(MMU_VRAMcntSaved, 0, sizeof(MMU_VRAMcntSaved[0])*10);
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FIFOclear(&MMU.fifos[0]);
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FIFOclear(&MMU.fifos[1]);
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@ -355,6 +361,96 @@ void MMU_clearMem()
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rtcInit();
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}
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// temporary implementations for clearing VRAM (garbage on screen)
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// TODO: rewrite VRAM control
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static u8 MMU_checkVRAM(u8 block, u8 val)
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{
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u32 size = 0;
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u8 *destination = NULL;
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if ((val & 0x80))
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{
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MMU_VRAMcntSaved[block] = val;
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return 1;
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}
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if (MMU_VRAMcntSaved[block] == 0) return 2;
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switch (MMU_VRAMcntSaved[block] & 0x07)
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{
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case 0:
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break;
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case 1:
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switch (block)
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{
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case 0: // A
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case 1: // B
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case 2: // C
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case 3: // D
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size = 0x20000 ;
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destination = ARM9Mem.ARM9_ABG + ((MMU_VRAMcntSaved[block] >> 3) & 3) * 0x20000 ;
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break;
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case 4: // E
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size = 0x10000;
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destination = ARM9Mem.ARM9_ABG ;
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break;
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case 5: // F
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case 6: // G
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size = 0x4000;
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destination = ARM9Mem.ARM9_ABG +
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(((MMU_VRAMcntSaved[block] >> 3) & 0x01) * 0x4000) +
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(((MMU_VRAMcntSaved[block] >> 4) & 0x1) * 0x10000) ;
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break;
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case 8: // H
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size = 0x8000;
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destination = ARM9Mem.ARM9_BBG ;
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break;
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case 9: // I
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size = 0x4000;
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destination = ARM9Mem.ARM9_BBG + 0x8000;
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break ;
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}
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break;
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case 2:
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switch(block)
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{
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case 0:
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case 1:
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// banks A,B are in use for OBJ at AOBJ + ofs * 0x20000
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size = 0x20000;
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destination = ARM9Mem.ARM9_AOBJ+(((MMU_VRAMcntSaved[block]>>3)&1)*0x20000);
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break;
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case 4: // E
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size = 0x10000;
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destination = ARM9Mem.ARM9_AOBJ;
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break;
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case 5:
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case 6:
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size = 0x4000;
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destination = ARM9Mem.ARM9_AOBJ+
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(((MMU_VRAMcntSaved[block]>>3)&1)*0x4000)+
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(((MMU_VRAMcntSaved[block]>>4)&1)*0x10000);
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break;
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}
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break;
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case 4:
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switch(block)
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{
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case 2: // C
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size = 0x20000;
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destination = ARM9Mem.ARM9_BBG ;
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break ;
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case 3: // D
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size = 0x20000;
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break ;
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}
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break;
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}
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if (!destination) return 3;
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memset(destination, 0, size) ;
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return 0;
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}
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/* the VRAM blocks keep their content even when not blended in */
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/* to ensure that we write the content back to the LCD ram */
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/* FIXME: VRAM Bank E,F,G,H,I missing */
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@ -485,10 +581,6 @@ static void MMU_VRAMWriteBackToLCD(u8 block)
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if (!destination) return ;
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if (!source) return ;
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memcpy(destination,source,size) ;
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//zero 10/10/08 - if vram is not mapped, then when it is read from, it should be zero
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//mimic this by clearing it now.
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memset(source,0,size) ;
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}
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static void MMU_VRAMReloadFromLCD(u8 block,u8 VRAMBankCnt)
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@ -1091,6 +1183,8 @@ void FASTCALL _MMU_write8(u32 adr, u8 val)
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case REG_VRAMCNTD:
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if(proc == ARMCPU_ARM9)
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{
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if (MMU_checkVRAM(adr-REG_VRAMCNTA, val) == 1) break;
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MMU_VRAMWriteBackToLCD(adr-REG_VRAMCNTA) ;
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switch(val & 0x1F)
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{
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