fix mario kart boot regression by readding support for arm7 shared vram banks. it still has some bg mapping issues, but it shares that in common with many games right now
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@ -209,7 +209,8 @@ u8 * MMU_struct::MMU_MEM[2][256] = {
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/* 4X*/ DUP8(MMU.ARM7_REG),
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DUP8(MMU.ARM7_WIRAM),
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/* 5X*/ DUP16(MMU.UNUSED_RAM),
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/* 6X*/ DUP16(MMU.UNUSED_RAM),
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/* 6X*/ DUP8(0), //this gets handled by special logic
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DUP8(ARM9Mem.ARM9_LCD),
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/* 7X*/ DUP16(MMU.UNUSED_RAM),
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/* 8X*/ DUP16(NULL),
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/* 9X*/ DUP16(NULL),
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@ -254,7 +255,8 @@ u32 MMU_struct::MMU_MASK[2][256] = {
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/* 4X*/ DUP8(0x00FFFFFF),
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DUP8(0x0000FFFF),
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/* 5X*/ DUP16(0x00000003),
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/* 6X*/ DUP16(0x00000003),
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/* 6X*/ DUP8(0x00000003),
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DUP8(0x000FFFFF),
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/* 7X*/ DUP16(0x00000003),
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/* 8X*/ DUP16(ROM_MASK),
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/* 9X*/ DUP16(ROM_MASK),
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@ -296,6 +298,9 @@ u8 vram_lcdc_map[VRAM_LCDC_PAGES];
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#define VRAM_ARM9_PAGES 512
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u8 vram_arm9_map[VRAM_ARM9_PAGES];
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//this chooses which banks are mapped in the 128K banks starting at 0x06000000 in ARM7
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u8 vram_arm7_map[2];
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//----->
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//consider these later, for better recordkeeping, instead of using the u8* in ARM9Mem
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@ -345,6 +350,9 @@ static const TVramBankInfo vram_bank_info[VRAM_BANKS] = {
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//maps an ARM9 BG/OBJ or LCDC address into an LCDC address, and informs the caller of whether it isn't mapped
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//TODO - in cases where this does some mapping work, we could bypass the logic at the end of the _read* and _write* routines
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//this is a good optimization to consider
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template<int PROCNUM>
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static FORCEINLINE u32 MMU_LCDmap(u32 addr, bool& unmapped)
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{
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unmapped = false;
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@ -353,6 +361,19 @@ static FORCEINLINE u32 MMU_LCDmap(u32 addr, bool& unmapped)
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if(addr < 0x06000000) return addr;
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if(addr >= 0x07000000) return addr;
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//shared wram mapping for arm7
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if(PROCNUM==ARMCPU_ARM7)
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{
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u32 ofs = addr & 0x1FFFF;
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u32 bank = (addr >> 17)&1;
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if(vram_arm7_map[bank] == VRAM_PAGE_UNMAPPED)
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{
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unmapped = true;
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return 0;
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}
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return 0x06800000 + (vram_arm7_map[bank]<<17) + ofs;
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}
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//handle LCD memory mirroring
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if(addr>=0x068A4000)
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addr = 0x06800000 +
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@ -399,7 +420,7 @@ u8 *MMU_RenderMapToLCD(u32 vram_addr)
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//this needs to go through a system like what is used for textures for mapping into chunks
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bool unmapped;
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vram_addr = MMU_LCDmap(vram_addr,unmapped);
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vram_addr = MMU_LCDmap<0>(vram_addr,unmapped);
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if(unmapped) return 0;
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else return ARM9Mem.ARM9_LCD + (vram_addr - 0x06800000);
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}
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@ -506,9 +527,17 @@ static inline void MMU_VRAMmapRefreshBank(const int bank)
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MMU_vram_arm9(bank,VRAM_PAGE_ABG+ofs*8);
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break;
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case 2: //arm7
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//MMU_vram_lcdc(bank); ?
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if(bank == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
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if(bank == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
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switch(ofs) {
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case 0:
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case 1:
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vram_arm7_map[ofs] = vram_bank_info[bank].page_addr;
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break;
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default:
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PROGINFO("Unsupported ofs setting %d for arm7 vram bank %c\n", ofs, 'A'+bank);
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}
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break;
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case 3: //texture
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ARM9Mem.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
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@ -655,6 +684,9 @@ unsupported_mst:
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void MMU_VRAM_unmap_all()
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{
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vram_arm7_map[0] = VRAM_PAGE_UNMAPPED;
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vram_arm7_map[1] = VRAM_PAGE_UNMAPPED;
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for(int i=0;i<VRAM_LCDC_PAGES;i++)
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vram_lcdc_map[i] = VRAM_PAGE_UNMAPPED;
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for(int i=0;i<VRAM_ARM9_PAGES;i++)
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@ -1843,7 +1875,7 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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}
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bool unmapped;
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adr = MMU_LCDmap(adr, unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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@ -2428,7 +2460,7 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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}
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bool unmapped;
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adr = MMU_LCDmap(adr, unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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@ -3007,7 +3039,7 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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}
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bool unmapped;
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adr = MMU_LCDmap(adr, unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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@ -3042,7 +3074,7 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr)
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#endif
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bool unmapped;
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adr = MMU_LCDmap(adr, unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return 0;
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return MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF]];
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@ -3123,7 +3155,7 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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}
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bool unmapped;
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adr = MMU_LCDmap(adr,unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped);
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if(unmapped) return 0;
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
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@ -3322,7 +3354,7 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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}
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bool unmapped;
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adr = MMU_LCDmap(adr,unmapped);
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped);
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if(unmapped) return 0;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
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@ -3376,6 +3408,10 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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#endif
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if ( adr == REG_RTC ) rtcWrite(val);
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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#ifdef _MMU_DEBUG
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mmu_log_debug_ARM7(adr, "(write08) %0x%X", val);
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@ -3803,6 +3839,10 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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return;
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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@ -4088,6 +4128,10 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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return;
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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@ -4122,6 +4166,10 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
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MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]]);
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#endif
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return 0;
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return MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]];
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}
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//================================================= MMU ARM7 read 16
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@ -4189,6 +4237,10 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return 0;
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/* Returns data from memory */
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
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}
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@ -4300,6 +4352,10 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return 0;
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//Returns data from memory
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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