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core: 

- optimization in ipc fifo;
This commit is contained in:
mtabachenko 2009-01-05 14:23:43 +00:00
parent fb160ff827
commit d501721848
7 changed files with 122 additions and 100 deletions
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14
desmume/README.WIN
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@ -63,14 +63,14 @@ change):
Left arrow - Left Left arrow - Left
Down arrow - Down Down arrow - Down
right arrow - Right right arrow - Right
v - A button x - A button
b - B button z - B button
g - X button s - X button
h - Y button a - Y button
c - Left Trigger w - Left Trigger
n - Right Trigger Q - Right Trigger
Enter - Start button Enter - Start button
Space - Select button Right Shift - Select button
Sound Settings: Sound Settings:
Here you can change the default sound settings. By default Here you can change the default sound settings. By default

123
desmume/src/FIFO.cpp
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@ -29,101 +29,112 @@
#include "MMU.h" #include "MMU.h"
// ========================================================= IPC FIFO // ========================================================= IPC FIFO
IPC_FIFO ipc_fifo; IPC_FIFO ipc_fifo[2]; // 0 - ARM9
// 1 - ARM7
void IPC_FIFOclear() void IPC_FIFOinit(u8 proc)
{ {
memset(&ipc_fifo, 0, sizeof(IPC_FIFO)); ipc_fifo[proc].head = 0;
//LOG("FIFO is cleared\n"); ipc_fifo[proc].tail = 0;
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, 0x00000101);
NDS_makeInt(proc^1, 18);
} }
#define FIFO_IS_FULL(proc) ((ipc_fifo[proc].head) && (ipc_fifo[proc].head == ipc_fifo[proc].tail+1)) ||\
((!ipc_fifo[proc].head) && (ipc_fifo[proc].tail == 15))
void IPC_FIFOsend(u8 proc, u32 val) void IPC_FIFOsend(u8 proc, u32 val)
{ {
//LOG("IPC%s send FIFO 0x%08X\n", proc?"7":"9", val);
u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184); u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
if (!(cnt_l & 0x8000)) return; // FIFO disabled if (!(cnt_l & 0x8000)) return; // FIFO disabled
u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
if (ipc_fifo.sendTail[proc] < 16) // last full == error if (FIFO_IS_FULL(proc)) // FIFO error
{ {
ipc_fifo.sendBuf[proc][ipc_fifo.sendTail[proc]] = val; cnt_l |= 0x4000;
ipc_fifo.sendTail[proc]++; T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
if (ipc_fifo.sendTail[proc] == 16) cnt_l |= 0x02; // full return;
cnt_l &= 0xFFFE;
if (ipc_fifo.recvTail[proc^1] < 16) // last full == error
{
ipc_fifo.recvBuf[proc^1][ipc_fifo.recvTail[proc^1]] = val;
ipc_fifo.recvTail[proc^1]++;
if (ipc_fifo.recvTail[proc^1] == 16) cnt_r |= 0x0200; // full
cnt_r &= 0xFEFF;
}
else
cnt_r |= 0x4200;
} }
else
cnt_l |= 0x4002;
// save in mem u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
cnt_l &= 0xFFFE; // clear send empty bit
cnt_r &= 0xFEFF; // set recv empty bit
ipc_fifo[proc].buf[ipc_fifo[proc].tail] = val;
ipc_fifo[proc].tail++;
if (ipc_fifo[proc].tail == 16)
ipc_fifo[proc].tail = 0;
if (FIFO_IS_FULL(proc))
{
cnt_l |= 0x0002; // set send full bit
cnt_r |= 0x0200; // set recv full bit
}
//LOG("IPC%s send FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"7":"9", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r); T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
if ((cnt_r & (1<<10))) MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0400) << 8 );
NDS_makeInt(proc^1, 18);
} }
u32 IPC_FIFOrecv(u8 proc) u32 IPC_FIFOrecv(u8 proc)
{ {
//LOG("IPC%s recv FIFO:\n", proc?"7":"9");
u32 val = 0; u32 val = 0;
u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184); u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
if (!(cnt_l & 0x8000)) return (val); // FIFO disabled
if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO error
{
cnt_l |= 0x4000;
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
return (val);
}
u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184); u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
if (ipc_fifo.recvTail[proc] > 0) // not empty cnt_l &= 0xFFFD; // clear send full bit
cnt_r &= 0xFDFF; // set recv full bit
val = ipc_fifo[proc].buf[ipc_fifo[proc].head];
ipc_fifo[proc].head++;
if (ipc_fifo[proc].head == 16)
ipc_fifo[proc].head = 0;
if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO empty
{ {
val = ipc_fifo.recvBuf[proc][0]; cnt_l |= 0x0001;
for (int i = 0; i < ipc_fifo.recvTail[proc]; i++) cnt_r |= 0x0100;
ipc_fifo.recvBuf[proc][i] = ipc_fifo.recvBuf[proc][i+1];
ipc_fifo.recvTail[proc]--;
if (ipc_fifo.recvTail[proc] == 0) // empty
cnt_l |= 0x0100;
// remove from head
for (int i = 0; i < ipc_fifo.sendTail[proc^1]; i++)
ipc_fifo.sendBuf[proc^1][i] = ipc_fifo.sendBuf[proc^1][i+1];
ipc_fifo.sendTail[proc^1]--;
if (ipc_fifo.sendTail[proc^1] == 0) // empty
cnt_r |= 0x0001;
} }
else
cnt_l |= 0x4100;
//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"9":"7", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r); T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
if ((cnt_l & (1<<3))) MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0004) << 9 );
NDS_makeInt(proc, 19);
return (val); return (val);
} }
void IPC_FIFOcnt(u8 proc, u16 val) void IPC_FIFOcnt(u8 proc, u16 val)
{ {
//LOG("IPC%s FIFO context 0x%X\n", proc?"7":"9", val);
u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184); u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
cnt_r &= 0x3FFF;
cnt_r |= (val & 0x8000);
cnt_l &= ~0x8404; //LOG("IPC%s FIFO context 0x%X (local 0x%X)\n", proc?"7":"9", val, cnt_l);
cnt_l |= (val & 0x8404); if (val & 0x4008)
cnt_l &= (~(val & 0x4000));
if (val & 0x0008)
{ {
IPC_FIFOclear(); u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
cnt_l |= 0x0101; ipc_fifo[proc].head = 0;
ipc_fifo[proc].tail = 0;
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, (cnt_l & 0x0301) | (val & 0x8404) | 1);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, (cnt_r & 0x8407) | 0x100);
MMU.reg_IF[proc] |= ((cnt_l & 0x0004) << 16);
return;
} }
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
if ((cnt_l & 0x0004)) T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l | (val & 0xBFF4));
NDS_makeInt(proc, 18); T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
MMU.reg_IF[proc] |= ((cnt_l & 0x0004) << 16);
} }
// ========================================================= GFX FIFO // ========================================================= GFX FIFO

11
desmume/src/FIFO.h
View File

@ -29,15 +29,14 @@
//=================================================== IPC FIFO //=================================================== IPC FIFO
typedef struct typedef struct
{ {
u32 sendBuf[2][16]; u32 buf[16];
u32 recvBuf[2][16];
u8 sendTail[2]; u8 head;
u8 recvTail[2]; u8 tail;
} IPC_FIFO; } IPC_FIFO;
extern IPC_FIFO ipc_fifo; extern IPC_FIFO ipc_fifo[2];
extern void IPC_FIFOclear(); extern void IPC_FIFOinit(u8 proc);
extern void IPC_FIFOsend(u8 proc, u32 val); extern void IPC_FIFOsend(u8 proc, u32 val);
extern u32 IPC_FIFOrecv(u8 proc); extern u32 IPC_FIFOrecv(u8 proc);
extern void IPC_FIFOcnt(u8 proc, u16 val); extern void IPC_FIFOcnt(u8 proc, u16 val);

46
desmume/src/MMU.cpp
View File

@ -361,7 +361,8 @@ void MMU_Init(void) {
MMU.DTCMRegion = 0x027C0000; MMU.DTCMRegion = 0x027C0000;
MMU.ITCMRegion = 0x00000000; MMU.ITCMRegion = 0x00000000;
IPC_FIFOclear(); IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
GFX_FIFOclear(); GFX_FIFOclear();
mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */ mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
@ -416,8 +417,9 @@ void MMU_clearMem()
memset(MMU.ARM7_ERAM, 0, 0x010000); memset(MMU.ARM7_ERAM, 0, 0x010000);
memset(MMU.ARM7_REG, 0, 0x010000); memset(MMU.ARM7_REG, 0, 0x010000);
IPC_FIFOclear(); IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
GFX_FIFOclear(); GFX_FIFOclear();
MMU.DTCMRegion = 0x027C0000; MMU.DTCMRegion = 0x027C0000;
@ -1446,6 +1448,22 @@ struct armcpu_memory_iface arm9_direct_memory_iface = {
arm9_write32 arm9_write32
}; };
static INLINE void MMU_IPCSync(u8 proc, u32 val)
{
//INFO("IPC%s sync 0x%08X\n", proc?"7":"9", val);
u32 IPCSYNC_local = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|((val>>8)&0xf);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
if ((val & 0x2000) && (IPCSYNC_remote & 0x4000))
NDS_makeInt(proc^1, 17);
}
//================================================================================================== ARM9 * //================================================================================================== ARM9 *
//========================================================================================================= //=========================================================================================================
//========================================================================================================= //=========================================================================================================
@ -1635,22 +1653,6 @@ static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val; MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
} }
static INLINE void MMU_IPCSync(u8 proc, u32 val)
{
//INFO("IPC%s sync 0x%08X\n", proc?"7":"9", val);
u32 IPCSYNC_local = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|((val>>8)&0xf);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
if ((val & 0x2000) && (IPCSYNC_remote & 0x4000))
NDS_makeInt(proc^1, 17);
}
//================================================= MMU ARM9 write 16 //================================================= MMU ARM9 write 16
static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val) static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
{ {
@ -2866,7 +2868,7 @@ static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
case REG_IF : case REG_IF :
return MMU.reg_IF[ARMCPU_ARM9]; return MMU.reg_IF[ARMCPU_ARM9];
case REG_IPCFIFORECV : case REG_IPCFIFORECV :
return IPC_FIFOrecv(ARMCPU_ARM9); return IPC_FIFOrecv(ARMCPU_ARM7);
case REG_TM0CNTL : case REG_TM0CNTL :
case REG_TM1CNTL : case REG_TM1CNTL :
case REG_TM2CNTL : case REG_TM2CNTL :
@ -3462,7 +3464,7 @@ static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
return; return;
case REG_IPCFIFOSEND : case REG_IPCFIFOSEND :
IPC_FIFOsend(ARMCPU_ARM7, val); IPC_FIFOsend(ARMCPU_ARM7, val);
return; return;
case REG_DMA0CNTL : case REG_DMA0CNTL :
//LOG("32 bit dma0 %04X\r\n", val); //LOG("32 bit dma0 %04X\r\n", val);
@ -3692,7 +3694,7 @@ static u32 FASTCALL _MMU_ARM7_read32(u32 adr)
case REG_IF : case REG_IF :
return MMU.reg_IF[ARMCPU_ARM7]; return MMU.reg_IF[ARMCPU_ARM7];
case REG_IPCFIFORECV : case REG_IPCFIFORECV :
return IPC_FIFOrecv(ARMCPU_ARM7); return IPC_FIFOrecv(ARMCPU_ARM9);
case REG_TM0CNTL : case REG_TM0CNTL :
case REG_TM1CNTL : case REG_TM1CNTL :
case REG_TM2CNTL : case REG_TM2CNTL :

14
desmume/src/NDSSystem.cpp
View File

@ -40,6 +40,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#include "./windows/disView.h" #include "./windows/disView.h"
#endif #endif
//#define USE_REAL_BIOS
static BOOL LidClosed = FALSE; static BOOL LidClosed = FALSE;
static u8 LidKeyCount = 0; static u8 LidKeyCount = 0;
@ -550,7 +552,11 @@ void NDS_Reset( void)
//_MMU_write32[ARMCPU_ARM9](0x02007FFC, 0xE92D4030); //_MMU_write32[ARMCPU_ARM9](0x02007FFC, 0xE92D4030);
//ARM7 BIOS IRQ HANDLER //ARM7 BIOS IRQ HANDLER
//inf = fopen("BiosNds7.ROM","rb"); #ifdef USE_REAL_BIOS
inf = fopen("BiosNds7.ROM","rb");
#else
inf = NULL;
#endif
if(inf) { if(inf) {
fread(MMU.ARM7_BIOS,1,16384,inf); fread(MMU.ARM7_BIOS,1,16384,inf);
fclose(inf); fclose(inf);
@ -569,7 +575,11 @@ void NDS_Reset( void)
} }
//ARM9 BIOS IRQ HANDLER //ARM9 BIOS IRQ HANDLER
//inf = fopen("BiosNds9.ROM","rb"); #ifdef USE_REAL_BIOS
inf = fopen("BiosNds9.ROM","rb");
#else
inf = NULL;
#endif
if(inf) { if(inf) {
fread(ARM9Mem.ARM9_BIOS,1,4096,inf); fread(ARM9Mem.ARM9_BIOS,1,4096,inf);
fclose(inf); fclose(inf);

12
desmume/src/saves.cpp
View File

@ -220,12 +220,12 @@ SFORMAT SF_MMU[]={
{ "MCHD", 4, 1, &MMU.CheckDMAs}, { "MCHD", 4, 1, &MMU.CheckDMAs},
//fifos //fifos
{ "F0ST", 1, 1, ipc_fifo.sendTail}, { "F0TL", 1, 1, &ipc_fifo[0].tail},
{ "F0RT", 1, 1, ipc_fifo.recvTail}, { "F0HD", 1, 1, &ipc_fifo[0].head},
{ "FSB0", 4, 16, &ipc_fifo.sendBuf[0]}, { "F0BF", 4, 16, &ipc_fifo[0].buf[0]},
{ "FRB0", 4, 16, &ipc_fifo.recvBuf[0]}, { "F1TL", 1, 1, &ipc_fifo[1].tail},
{ "FSB1", 4, 16, &ipc_fifo.sendBuf[1]}, { "F1HD", 1, 1, &ipc_fifo[1].head},
{ "FRB1", 4, 16, &ipc_fifo.recvBuf[1]}, { "F1BF", 4, 16, &ipc_fifo[1].buf[0]},
{ 0 } { 0 }
}; };

2
desmume/src/windows/AboutBox.cpp
View File

@ -82,7 +82,7 @@ BOOL CALLBACK AboutBox_Proc (HWND dialog, UINT message,WPARAM wparam,LPARAM lpar
strcat((char *)scroll_buffer[i + PER_PAGE_TEAM], "\n"); strcat((char *)scroll_buffer[i + PER_PAGE_TEAM], "\n");
} }
SetTimer(dialog, ABOUT_TIMER_ID, 400, (TIMERPROC) NULL); SetTimer(dialog, ABOUT_TIMER_ID, 400, (TIMERPROC) NULL);
scroll_start = 0; scroll_start = 1;
break; break;
} }