parent
fb160ff827
commit
d501721848
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@ -63,14 +63,14 @@ change):
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Left arrow - Left
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Down arrow - Down
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right arrow - Right
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v - A button
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b - B button
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g - X button
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h - Y button
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c - Left Trigger
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n - Right Trigger
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x - A button
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z - B button
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s - X button
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a - Y button
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w - Left Trigger
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Q - Right Trigger
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Enter - Start button
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Space - Select button
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Right Shift - Select button
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Sound Settings:
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Here you can change the default sound settings. By default
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@ -29,101 +29,112 @@
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#include "MMU.h"
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// ========================================================= IPC FIFO
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IPC_FIFO ipc_fifo;
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IPC_FIFO ipc_fifo[2]; // 0 - ARM9
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// 1 - ARM7
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void IPC_FIFOclear()
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void IPC_FIFOinit(u8 proc)
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{
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memset(&ipc_fifo, 0, sizeof(IPC_FIFO));
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//LOG("FIFO is cleared\n");
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ipc_fifo[proc].head = 0;
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ipc_fifo[proc].tail = 0;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, 0x00000101);
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NDS_makeInt(proc^1, 18);
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}
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#define FIFO_IS_FULL(proc) ((ipc_fifo[proc].head) && (ipc_fifo[proc].head == ipc_fifo[proc].tail+1)) ||\
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((!ipc_fifo[proc].head) && (ipc_fifo[proc].tail == 15))
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void IPC_FIFOsend(u8 proc, u32 val)
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{
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//LOG("IPC%s send FIFO 0x%08X\n", proc?"7":"9", val);
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u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
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if (!(cnt_l & 0x8000)) return; // FIFO disabled
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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if (ipc_fifo.sendTail[proc] < 16) // last full == error
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if (FIFO_IS_FULL(proc)) // FIFO error
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{
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ipc_fifo.sendBuf[proc][ipc_fifo.sendTail[proc]] = val;
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ipc_fifo.sendTail[proc]++;
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if (ipc_fifo.sendTail[proc] == 16) cnt_l |= 0x02; // full
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cnt_l &= 0xFFFE;
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if (ipc_fifo.recvTail[proc^1] < 16) // last full == error
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{
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ipc_fifo.recvBuf[proc^1][ipc_fifo.recvTail[proc^1]] = val;
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ipc_fifo.recvTail[proc^1]++;
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if (ipc_fifo.recvTail[proc^1] == 16) cnt_r |= 0x0200; // full
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cnt_r &= 0xFEFF;
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}
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else
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cnt_r |= 0x4200;
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cnt_l |= 0x4000;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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return;
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}
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else
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cnt_l |= 0x4002;
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// save in mem
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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cnt_l &= 0xFFFE; // clear send empty bit
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cnt_r &= 0xFEFF; // set recv empty bit
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ipc_fifo[proc].buf[ipc_fifo[proc].tail] = val;
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ipc_fifo[proc].tail++;
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if (ipc_fifo[proc].tail == 16)
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ipc_fifo[proc].tail = 0;
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if (FIFO_IS_FULL(proc))
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{
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cnt_l |= 0x0002; // set send full bit
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cnt_r |= 0x0200; // set recv full bit
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}
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//LOG("IPC%s send FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"7":"9", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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if ((cnt_r & (1<<10)))
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NDS_makeInt(proc^1, 18);
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MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0400) << 8 );
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}
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u32 IPC_FIFOrecv(u8 proc)
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{
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//LOG("IPC%s recv FIFO:\n", proc?"7":"9");
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u32 val = 0;
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u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
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if (!(cnt_l & 0x8000)) return (val); // FIFO disabled
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if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO error
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{
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cnt_l |= 0x4000;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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return (val);
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}
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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if (ipc_fifo.recvTail[proc] > 0) // not empty
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cnt_l &= 0xFFFD; // clear send full bit
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cnt_r &= 0xFDFF; // set recv full bit
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val = ipc_fifo[proc].buf[ipc_fifo[proc].head];
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ipc_fifo[proc].head++;
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if (ipc_fifo[proc].head == 16)
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ipc_fifo[proc].head = 0;
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if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO empty
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{
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val = ipc_fifo.recvBuf[proc][0];
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for (int i = 0; i < ipc_fifo.recvTail[proc]; i++)
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ipc_fifo.recvBuf[proc][i] = ipc_fifo.recvBuf[proc][i+1];
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ipc_fifo.recvTail[proc]--;
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if (ipc_fifo.recvTail[proc] == 0) // empty
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cnt_l |= 0x0100;
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// remove from head
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for (int i = 0; i < ipc_fifo.sendTail[proc^1]; i++)
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ipc_fifo.sendBuf[proc^1][i] = ipc_fifo.sendBuf[proc^1][i+1];
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ipc_fifo.sendTail[proc^1]--;
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if (ipc_fifo.sendTail[proc^1] == 0) // empty
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cnt_r |= 0x0001;
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cnt_l |= 0x0001;
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cnt_r |= 0x0100;
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}
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else
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cnt_l |= 0x4100;
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//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"9":"7", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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if ((cnt_l & (1<<3)))
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NDS_makeInt(proc, 19);
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MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0004) << 9 );
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return (val);
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}
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void IPC_FIFOcnt(u8 proc, u16 val)
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{
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//LOG("IPC%s FIFO context 0x%X\n", proc?"7":"9", val);
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u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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cnt_r &= 0x3FFF;
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cnt_r |= (val & 0x8000);
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cnt_l &= ~0x8404;
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cnt_l |= (val & 0x8404);
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cnt_l &= (~(val & 0x4000));
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if (val & 0x0008)
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//LOG("IPC%s FIFO context 0x%X (local 0x%X)\n", proc?"7":"9", val, cnt_l);
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if (val & 0x4008)
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{
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IPC_FIFOclear();
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cnt_l |= 0x0101;
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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ipc_fifo[proc].head = 0;
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ipc_fifo[proc].tail = 0;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, (cnt_l & 0x0301) | (val & 0x8404) | 1);
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, (cnt_r & 0x8407) | 0x100);
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MMU.reg_IF[proc] |= ((cnt_l & 0x0004) << 16);
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return;
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}
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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if ((cnt_l & 0x0004))
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NDS_makeInt(proc, 18);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l | (val & 0xBFF4));
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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MMU.reg_IF[proc] |= ((cnt_l & 0x0004) << 16);
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}
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// ========================================================= GFX FIFO
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//=================================================== IPC FIFO
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typedef struct
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{
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u32 sendBuf[2][16];
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u32 recvBuf[2][16];
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u32 buf[16];
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u8 sendTail[2];
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u8 recvTail[2];
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u8 head;
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u8 tail;
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} IPC_FIFO;
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extern IPC_FIFO ipc_fifo;
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extern void IPC_FIFOclear();
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extern IPC_FIFO ipc_fifo[2];
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extern void IPC_FIFOinit(u8 proc);
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extern void IPC_FIFOsend(u8 proc, u32 val);
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extern u32 IPC_FIFOrecv(u8 proc);
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extern void IPC_FIFOcnt(u8 proc, u16 val);
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@ -361,7 +361,8 @@ void MMU_Init(void) {
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MMU.DTCMRegion = 0x027C0000;
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MMU.ITCMRegion = 0x00000000;
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IPC_FIFOclear();
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IPC_FIFOinit(ARMCPU_ARM9);
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IPC_FIFOinit(ARMCPU_ARM7);
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GFX_FIFOclear();
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mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
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@ -416,8 +417,9 @@ void MMU_clearMem()
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memset(MMU.ARM7_ERAM, 0, 0x010000);
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memset(MMU.ARM7_REG, 0, 0x010000);
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IPC_FIFOclear();
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IPC_FIFOinit(ARMCPU_ARM9);
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IPC_FIFOinit(ARMCPU_ARM7);
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GFX_FIFOclear();
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MMU.DTCMRegion = 0x027C0000;
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@ -1446,6 +1448,22 @@ struct armcpu_memory_iface arm9_direct_memory_iface = {
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arm9_write32
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};
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static INLINE void MMU_IPCSync(u8 proc, u32 val)
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{
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//INFO("IPC%s sync 0x%08X\n", proc?"7":"9", val);
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u32 IPCSYNC_local = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
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u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
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IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
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IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|((val>>8)&0xf);
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
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T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
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if ((val & 0x2000) && (IPCSYNC_remote & 0x4000))
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NDS_makeInt(proc^1, 17);
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}
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//================================================================================================== ARM9 *
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//=========================================================================================================
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//=========================================================================================================
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@ -1635,22 +1653,6 @@ static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
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}
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static INLINE void MMU_IPCSync(u8 proc, u32 val)
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{
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//INFO("IPC%s sync 0x%08X\n", proc?"7":"9", val);
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u32 IPCSYNC_local = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
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u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
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IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
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IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|((val>>8)&0xf);
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
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T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
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if ((val & 0x2000) && (IPCSYNC_remote & 0x4000))
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NDS_makeInt(proc^1, 17);
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}
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//================================================= MMU ARM9 write 16
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static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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{
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@ -2866,7 +2868,7 @@ static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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case REG_IF :
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return MMU.reg_IF[ARMCPU_ARM9];
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case REG_IPCFIFORECV :
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return IPC_FIFOrecv(ARMCPU_ARM9);
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return IPC_FIFOrecv(ARMCPU_ARM7);
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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@ -3462,7 +3464,7 @@ static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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return;
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case REG_IPCFIFOSEND :
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IPC_FIFOsend(ARMCPU_ARM7, val);
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IPC_FIFOsend(ARMCPU_ARM7, val);
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return;
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case REG_DMA0CNTL :
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//LOG("32 bit dma0 %04X\r\n", val);
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@ -3692,7 +3694,7 @@ static u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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case REG_IF :
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return MMU.reg_IF[ARMCPU_ARM7];
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case REG_IPCFIFORECV :
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return IPC_FIFOrecv(ARMCPU_ARM7);
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return IPC_FIFOrecv(ARMCPU_ARM9);
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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|
|
|
@ -40,6 +40,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
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#include "./windows/disView.h"
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#endif
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||||
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||||
//#define USE_REAL_BIOS
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static BOOL LidClosed = FALSE;
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static u8 LidKeyCount = 0;
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|
@ -550,7 +552,11 @@ void NDS_Reset( void)
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//_MMU_write32[ARMCPU_ARM9](0x02007FFC, 0xE92D4030);
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||||
//ARM7 BIOS IRQ HANDLER
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||||
//inf = fopen("BiosNds7.ROM","rb");
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#ifdef USE_REAL_BIOS
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inf = fopen("BiosNds7.ROM","rb");
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||||
#else
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inf = NULL;
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||||
#endif
|
||||
if(inf) {
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fread(MMU.ARM7_BIOS,1,16384,inf);
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fclose(inf);
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||||
|
@ -569,7 +575,11 @@ void NDS_Reset( void)
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}
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||||
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||||
//ARM9 BIOS IRQ HANDLER
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||||
//inf = fopen("BiosNds9.ROM","rb");
|
||||
#ifdef USE_REAL_BIOS
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||||
inf = fopen("BiosNds9.ROM","rb");
|
||||
#else
|
||||
inf = NULL;
|
||||
#endif
|
||||
if(inf) {
|
||||
fread(ARM9Mem.ARM9_BIOS,1,4096,inf);
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||||
fclose(inf);
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||||
|
|
|
@ -220,12 +220,12 @@ SFORMAT SF_MMU[]={
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|||
{ "MCHD", 4, 1, &MMU.CheckDMAs},
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||||
//fifos
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{ "F0ST", 1, 1, ipc_fifo.sendTail},
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{ "F0RT", 1, 1, ipc_fifo.recvTail},
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{ "FSB0", 4, 16, &ipc_fifo.sendBuf[0]},
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{ "FRB0", 4, 16, &ipc_fifo.recvBuf[0]},
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{ "FSB1", 4, 16, &ipc_fifo.sendBuf[1]},
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{ "FRB1", 4, 16, &ipc_fifo.recvBuf[1]},
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{ "F0TL", 1, 1, &ipc_fifo[0].tail},
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||||
{ "F0HD", 1, 1, &ipc_fifo[0].head},
|
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{ "F0BF", 4, 16, &ipc_fifo[0].buf[0]},
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{ "F1TL", 1, 1, &ipc_fifo[1].tail},
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{ "F1HD", 1, 1, &ipc_fifo[1].head},
|
||||
{ "F1BF", 4, 16, &ipc_fifo[1].buf[0]},
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{ 0 }
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||||
};
|
||||
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||||
|
|
|
@ -82,7 +82,7 @@ BOOL CALLBACK AboutBox_Proc (HWND dialog, UINT message,WPARAM wparam,LPARAM lpar
|
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strcat((char *)scroll_buffer[i + PER_PAGE_TEAM], "\n");
|
||||
}
|
||||
SetTimer(dialog, ABOUT_TIMER_ID, 400, (TIMERPROC) NULL);
|
||||
scroll_start = 0;
|
||||
scroll_start = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue