0.9.4+ branch: revert changes in r2881, that was unreliable.
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@ -1018,19 +1018,19 @@ static void loadstate()
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_MMU_write16<ARMCPU_ARM9>(0x04000304, _MMU_read16<ARMCPU_ARM9>(0x04000304));
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// This should regenerate the graphics configuration
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for (int i = REG_BASE_DISPA; i<=REG_BASE_DISPA + 0x66; i+=2)
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_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
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for (int i = REG_BASE_DISPB; i<=REG_BASE_DISPB + 0x7F; i+=2)
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_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
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//zero 27-jul-09 : was formerly up to 7F but that wrote to dispfifo which is dumb (one of nitsuja's desynch bugs [that he found, not caused])
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//so then i brought it down to 66 but this resulted in a conceptual bug with affine start registers, which shouldnt get regenerated
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//so then i just made this exhaustive list
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// for (int i = REG_BASE_DISPA; i<=REG_BASE_DISPA + 0x66; i+=2)
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//_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
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// for (int i = REG_BASE_DISPB; i<=REG_BASE_DISPB + 0x7F; i+=2)
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//_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
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static const u8 mainRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x64,0x66,0x6c};
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static const u8 subRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x6c};
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for(u32 i=0;i<ARRAY_SIZE(mainRegenAddr);i++)
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_MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i]));
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for(u32 i=0;i<ARRAY_SIZE(subRegenAddr);i++)
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_MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i]));
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//static const u8 mainRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x64,0x66,0x6c};
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//static const u8 subRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x6c};
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//for(u32 i=0;i<ARRAY_SIZE(mainRegenAddr);i++)
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// _MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i]));
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//for(u32 i=0;i<ARRAY_SIZE(subRegenAddr);i++)
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// _MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i]));
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// no need to restore 0x60 since control and MMU.ARM9_REG are both in the savestates, and restoring it could mess up the ack bits anyway
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SetupMMU(nds.debugConsole);
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