+ Fixed LDR*/STR* opcodes (and other minor fixes) on the ARM core
+ Fixed unaligned memory access on THUMB Core
This commit is contained in:
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@ -1,8 +1,13 @@
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/* Copyright (C) 2006 yopyop
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/*
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Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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yopyop156.ifrance.com
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This file is part of DeSmuME
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Code added on 18/08/2006 by shash
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- Missing missaligned addresses correction
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(reference in http://nocash.emubase.de/gbatek.htm#cpumemoryalignments)
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This file is part of DeSmuME
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DeSmuME is free software; you can redistribute it and/or modify
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DeSmuME is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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@ -390,7 +395,7 @@ static u32 FASTCALL OP_NEG(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 a = cpu->R[REG_NUM(i, 3)];
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u32 a = cpu->R[REG_NUM(i, 3)];
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cpu->R[REG_NUM(i, 0)] = -a;
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cpu->R[REG_NUM(i, 0)] = -((signed int)a);
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
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cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
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@ -471,7 +476,7 @@ static u32 FASTCALL OP_MVN(armcpu_t *cpu)
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static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
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static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u8 Rd = (i&7) | ((i>>4)&8);
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u32 Rd = (i&7) | ((i>>4)&8);
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cpu->R[Rd] += cpu->R[REG_POS(i, 3)];
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cpu->R[Rd] += cpu->R[REG_POS(i, 3)];
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if(Rd==15)
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if(Rd==15)
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@ -483,7 +488,7 @@ static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
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static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
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static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u8 Rn = (i&7) | ((i>>4)&8);
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u32 Rn = (i&7) | ((i>>4)&8);
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u32 tmp = cpu->R[Rn] -cpu->R[REG_POS(i, 3)];
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u32 tmp = cpu->R[Rn] -cpu->R[REG_POS(i, 3)];
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cpu->CPSR.bits.N = BIT31(tmp);
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cpu->CPSR.bits.N = BIT31(tmp);
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@ -497,7 +502,7 @@ static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
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static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu)
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static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u8 Rd = (i&7) | ((i>>4)&8);
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u32 Rd = (i&7) | ((i>>4)&8);
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cpu->R[Rd] = cpu->R[REG_POS(i, 3)];
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cpu->R[Rd] = cpu->R[REG_POS(i, 3)];
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if(Rd==15)
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if(Rd==15)
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@ -531,11 +536,11 @@ static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu)
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static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu)
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static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu)
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{
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{
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u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2);
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u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2);
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cpu->R[REG_NUM(cpu->instruction, 8)] = MMU_readWord(cpu->proc_ID, adr);
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cpu->R[REG_NUM(cpu->instruction, 8)] = MMU_readWord(cpu->proc_ID, adr);
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu)
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static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu)
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@ -577,8 +582,12 @@ static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu)
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static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu)
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static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
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u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
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cpu->R[REG_NUM(i, 0)] = MMU_readWord(cpu->proc_ID, adr);
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u32 tempValue = MMU_readWord(cpu->proc_ID, adr&0xFFFFFFFC);
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adr = (adr&3)*8;
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tempValue = (tempValue>>adr) | (tempValue<<(32-adr));
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cpu->R[REG_NUM(i, 0)] = tempValue;
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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@ -623,7 +632,10 @@ static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
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cpu->R[REG_NUM(i, 0)] = MMU_readWord(cpu->proc_ID, adr);
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u32 tempValue = MMU_readWord(cpu->proc_ID, adr&0xFFFFFFFC);
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adr = (adr&3)*8;
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tempValue = (tempValue>>adr) | (tempValue<<(32-adr));
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cpu->R[REG_NUM(i, 0)] = tempValue;
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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@ -632,7 +644,7 @@ static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
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MMU_writeByte(cpu->proc_ID, adr, cpu->R[REG_NUM(i, 0)]);
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MMU_writeByte(cpu->proc_ID, adr, (u8)cpu->R[REG_NUM(i, 0)]);
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return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
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return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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@ -650,7 +662,7 @@ static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
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u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
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MMU_writeHWord(cpu->proc_ID, adr, cpu->R[REG_NUM(i, 0)]);
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MMU_writeHWord(cpu->proc_ID, adr, (u16)cpu->R[REG_NUM(i, 0)]);
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return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
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return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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@ -677,7 +689,7 @@ static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[13] + ((i&0xFF)<<2);
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u32 adr = cpu->R[13] + ((i&0xFF)<<2);
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cpu->R[REG_NUM(i, 8)] = MMU_readWord(cpu->proc_ID, adr);
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cpu->R[REG_NUM(i, 8)] = MMU_readWord(cpu->proc_ID, adr);
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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}
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}
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[13] - 4;
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u32 adr = cpu->R[13] - 4;
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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for(j = 0; j<8; ++j)
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for(j = 0; j<8; ++j)
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if(BIT_N(i, 7-j))
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if(BIT_N(i, 7-j))
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@ -735,8 +746,7 @@ static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[13] - 4;
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u32 adr = cpu->R[13] - 4;
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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MMU_writeWord(cpu->proc_ID, adr, cpu->R[14]);
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MMU_writeWord(cpu->proc_ID, adr, cpu->R[14]);
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c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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c += MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
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@ -758,8 +768,7 @@ static u32 FASTCALL OP_POP(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[13];
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u32 adr = cpu->R[13];
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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for(j = 0; j<8; ++j)
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for(j = 0; j<8; ++j)
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if(BIT_N(i, j))
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if(BIT_N(i, j))
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@ -777,8 +786,7 @@ static u32 FASTCALL OP_POP_PC(armcpu_t *cpu)
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[13];
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u32 adr = cpu->R[13];
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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for(j = 0; j<8; ++j)
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for(j = 0; j<8; ++j)
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if(BIT_N(i, j))
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if(BIT_N(i, j))
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 8)];
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u32 adr = cpu->R[REG_NUM(i, 8)];
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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for(j = 0; j<8; ++j)
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for(j = 0; j<8; ++j)
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if(BIT_N(i, j))
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if(BIT_N(i, j))
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{
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{
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u32 i = cpu->instruction;
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u32 i = cpu->instruction;
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u32 adr = cpu->R[REG_NUM(i, 8)];
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u32 adr = cpu->R[REG_NUM(i, 8)];
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u32 c = 0;
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u32 c = 0, j;
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u32 j;
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for(j = 0; j<8; ++j)
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for(j = 0; j<8; ++j)
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if(BIT_N(i, j))
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if(BIT_N(i, j))
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