tried to correct structures packing (so that they take desired size)
This commit is contained in:
damdoum
parent
2eb5656ce6
commit
cd488f63d6
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@ -205,7 +205,7 @@ void GPU_resortBGs(GPU *gpu)
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for (i=NB_BG,j=0; i>0; ) {
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i--;
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if (!gpu->LayersEnable[i]) continue;
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prio = gpu->dispx_st->dispx_BGxCNT[i].bits.Priority;
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prio = (gpu->dispx_st)->dispx_BGxCNT[i].bits.Priority;
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item = &(gpu->itemsForPriority[prio]);
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item->BGs[item->nbBGs]=i;
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item->nbBGs++;
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@ -237,10 +237,10 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
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BOOL LayersEnable[5];
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u16 WinBG=0;
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struct _DISPCNT * cnt;
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cnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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cnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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// cnt = &gpu->dispCnt.bits;
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gpu->dispx_st->dispx_DISPCNT.val = p;
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(gpu->dispx_st)->dispx_DISPCNT.val = p;
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// gpu->dispMode = DISPCNT_DISPLAY_MODE(p,gpu->lcd) ;
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gpu->dispMode = cnt->DisplayMode & ((gpu->core)?1:3);
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@ -303,11 +303,11 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
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/* FIXME: all DEBUG_TRI are broken */
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void GPU_setBGProp(GPU * gpu, u16 num, u16 p)
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{
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struct _BGxCNT * cnt = &(gpu->dispx_st->dispx_BGxCNT[num].bits), *cnt2;
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _BGxCNT * cnt = &((gpu->dispx_st)->dispx_BGxCNT[num].bits), *cnt2;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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int mode;
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gpu->dispx_st->dispx_BGxCNT[num].val = p;
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(gpu->dispx_st)->dispx_BGxCNT[num].val = p;
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GPU_resortBGs(gpu);
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@ -354,6 +354,23 @@ void GPU_remove(GPU * gpu, u8 num)
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}
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void GPU_addBack(GPU * gpu, u8 num)
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{
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REG_DISPx * r = gpu->dispx_st;
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printf ("%08x %08x\n", r, (long)(&r->dispx_DISPCNT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispA_DISPSTAT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_VCOUNT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[0]) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[1]) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[2]) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BGxCNT[3]) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BGxOFS[0]) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BG2PARMS) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_BG3PARMS) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_WINCNT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_MISC) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispA_DISP3DCNT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispA_DISPCAPCNT) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispA_DISPMMEMFIFO) - (long)r);
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printf ("\t%08x\n", (long)(&r->dispx_MASTERBRIGHT) - (long)r);
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if (num == 4) gpu->dispOBJ = 1;
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else gpu->dispBG[num] = 1;
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GPU_resortBGs(gpu);
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@ -548,7 +565,7 @@ INLINE BOOL withinRect (u8 x,u8 y, u16 startX, u16 startY, u16 endX, u16 endY)
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// setting some values twice
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void renderline_checkWindows(GPU *gpu, u8 bgnum, u16 x, u16 y, BOOL *draw, BOOL *effect)
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{
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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BOOL wwin0=0, wwin1=0, wwobj=0, windows=0;
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// Check if win0 if enabled, and only check if it is
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@ -710,8 +727,8 @@ INLINE BOOL renderline_setFinalColor(GPU *gpu,u32 passing,u8 bgnum,u8 *dst,u16 c
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/* render a text background to the combined pixelbuffer */
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INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 YBG, u16 LG)
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{
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struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits;
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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u16 lg = gpu->BGSize[num][0];
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u16 ht = gpu->BGSize[num][1];
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u16 tmp = ((YBG&(ht-1))>>3);
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@ -732,7 +749,7 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y
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if(tmp>31)
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{
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map+= ADDRESS_STEP_512B << bgCnt.ScreenSize ;
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map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ;
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}
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tile = (u8*) gpu->BG_tile_ram[num];
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@ -740,9 +757,9 @@ INLINE void renderline_textBG(GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG, u16 Y
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xoff = XBG;
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pal = ARM9Mem.ARM9_VMEM + gpu->core * ADDRESS_STEP_1KB ;
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if(!bgCnt.Palette_256) /* color: 16 palette entries */
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if(!bgCnt->Palette_256) /* color: 16 palette entries */
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{
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if (bgCnt.Mosaic_Enable){
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if (bgCnt->Mosaic_Enable){
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/* test NDS: #2 of
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http://desmume.sourceforge.net/forums/index.php?action=vthread&forum=2&topic=50&page=0#msg192 */
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@ -967,10 +984,10 @@ INLINE void rot_scale_op(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 P
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INLINE void apply_rot_fun(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, u16 LG, rot_fun fun, u8 * map, u8 * tile, u8 * pal)
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{
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struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits;
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struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
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s32 wh = gpu->BGSize[num][0];
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s32 ht = gpu->BGSize[num][1];
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rot_scale_op(gpu, num, dst, H, X, Y, PA, PB, PC, PD, LG, wh, ht, bgCnt.PaletteSet_Wrap, fun, map, tile, pal);
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rot_scale_op(gpu, num, dst, H, X, Y, PA, PB, PC, PD, LG, wh, ht, bgCnt->PaletteSet_Wrap, fun, map, tile, pal);
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}
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@ -984,13 +1001,13 @@ INLINE void rotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16
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INLINE void extRotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, s16 LG)
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{
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struct _BGxCNT bgCnt = gpu->dispx_st->dispx_BGxCNT[num].bits;
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struct _BGxCNT * bgCnt = &(gpu->dispx_st)->dispx_BGxCNT[num].bits;
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u8 *map, *tile, *pal;
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u8 affineModeSelection ;
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/* see: http://nocash.emubase.de/gbatek.htm#dsvideobgmodescontrol */
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affineModeSelection = (bgCnt.Palette_256 << 1) | (bgCnt.CharacBase_Block & 1) ;
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affineModeSelection = (bgCnt->Palette_256 << 1) | (bgCnt->CharacBase_Block & 1) ;
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// printf("extrot mode %d\n", affineModeSelection);
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switch(affineModeSelection)
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{
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@ -1028,26 +1045,38 @@ void lineText(GPU * gpu, u8 num, u16 l, u8 * DST)
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}
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void lineRot(GPU * gpu, u8 num, u16 l, u8 * DST)
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{
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{
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BGxPARMS * parms;
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if (num==2) {
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parms = &(gpu->dispx_st)->dispx_BG2PARMS;
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} else {
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parms = &(gpu->dispx_st)->dispx_BG3PARMS;
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}
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rotBG2(gpu, num, DST, l,
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gpu->BGX[num],
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gpu->BGY[num],
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gpu->BGPA[num],
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gpu->BGPB[num],
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gpu->BGPC[num],
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gpu->BGPD[num],
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parms->BGxX,
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parms->BGxY,
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parms->BGxPA,
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parms->BGxPB,
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parms->BGxPC,
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parms->BGxPD,
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256);
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}
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void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST)
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{
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BGxPARMS * parms;
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if (num==2) {
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parms = &(gpu->dispx_st)->dispx_BG2PARMS;
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} else {
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parms = &(gpu->dispx_st)->dispx_BG3PARMS;
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}
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extRotBG2(gpu, num, DST, l,
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gpu->BGX[num],
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gpu->BGY[num],
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gpu->BGPA[num],
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gpu->BGPB[num],
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gpu->BGPC[num],
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gpu->BGPD[num],
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parms->BGxX,
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parms->BGxY,
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parms->BGxPA,
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parms->BGxPB,
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parms->BGxPC,
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parms->BGxPD,
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256);
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}
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@ -1224,7 +1253,7 @@ INLINE void compute_sprite_rotoscale(GPU * gpu, _OAM_ * spriteInfo,
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void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
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{
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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_OAM_ * spriteInfo = (_OAM_ *)(gpu->oam + (nbShow-1));// + 127;
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u8 block = gpu->sprBoundary;
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u16 i;
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@ -1297,7 +1326,7 @@ void sprite1D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
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void sprite2D(GPU * gpu, u16 l, u8 * dst, u8 * prioTab)
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{
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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_OAM_ * spriteInfo = (_OAM_*)(gpu->oam + (nbShow-1));// + 127;
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u16 i;
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@ -1523,7 +1552,7 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
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{
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GPU * gpu = screen->gpu;
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struct _DISPCAPCNT * capcnt;
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struct _DISPCNT * dispCnt = &gpu->dispx_st->dispx_DISPCNT.bits;
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struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
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struct _MASTER_BRIGHT * mBright;
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u8 * dst = GPU_screen + (screen->offset + l) * 512;
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u8 * mdst = GPU_screen + (MainScreen.offset + l) * 512;
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@ -1748,7 +1777,7 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
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// Reference: http://nocash.emubase.de/gbatek.htm#dsvideo (Under MASTER_BRIGHTNESS)
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/* Mightymax> it should be more effective if the windowmanager applies brightness when drawing */
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/* it will most likly take acceleration, while we are stuck here with CPU power */
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mBright = &gpu->dispx_st->dispx_MASTERBRIGHT.bits;
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mBright = &(gpu->dispx_st)->dispx_MASTERBRIGHT.bits;
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switch (mBright->Mode)
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{
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// Disabled
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@ -43,44 +43,44 @@ extern "C" {
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struct _DISPCNT
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{
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/*0*/ unsigned BG_Mode:3; // A+B:
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/*3*/ unsigned BG0_3D:1; // A : 0=2D, 1=3D
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/*4*/ unsigned OBJ_Tile_1D:1; // A+B: 0=2D (32KB), 1=1D (32..256KB)
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/*5*/ unsigned OBJ_BMP_2D_dim:1; // A+B: 0=128x512, 1=256x256 pixels
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/*6*/ unsigned OBJ_BMP_mapping:1; // A+B: 0=2D (128KB), 1=1D (128..256KB)
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/* 0*/ u8 BG_Mode:3; // A+B:
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/* 3*/ u8 BG0_3D:1; // A : 0=2D, 1=3D
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/* 4*/ u8 OBJ_Tile_1D:1; // A+B: 0=2D (32KB), 1=1D (32..256KB)
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/* 5*/ u8 OBJ_BMP_2D_dim:1; // A+B: 0=128x512, 1=256x256 pixels
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/* 6*/ u8 OBJ_BMP_mapping:1; // A+B: 0=2D (128KB), 1=1D (128..256KB)
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// 7-15 same as GBA
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/*7*/ unsigned ForceBlank:1; // A+B:
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/*8*/ unsigned BG0_Enable:1; // A+B: 0=disable, 1=Enable
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/*9*/ unsigned BG1_Enable:1; // A+B: 0=disable, 1=Enable
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/*10*/ unsigned BG2_Enable:1; // A+B: 0=disable, 1=Enable
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/*11*/ unsigned BG3_Enable:1; // A+B: 0=disable, 1=Enable
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/*12*/ unsigned OBJ_Enable:1; // A+B: 0=disable, 1=Enable
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/*13*/ unsigned Win0_Enable:1; // A+B: 0=disable, 1=Enable
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/*14*/ unsigned Win1_Enable:1; // A+B: 0=disable, 1=Enable
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/*15*/ unsigned WinOBJ_Enable:1; // A+B: 0=disable, 1=Enable
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/* 7*/ u8 ForceBlank:1; // A+B:
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/* 8*/ u8 BG0_Enable:1; // A+B: 0=disable, 1=Enable
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/* 9*/ u8 BG1_Enable:1; // A+B: 0=disable, 1=Enable
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/*10*/ u8 BG2_Enable:1; // A+B: 0=disable, 1=Enable
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/*11*/ u8 BG3_Enable:1; // A+B: 0=disable, 1=Enable
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/*12*/ u8 OBJ_Enable:1; // A+B: 0=disable, 1=Enable
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/*13*/ u8 Win0_Enable:1; // A+B: 0=disable, 1=Enable
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/*14*/ u8 Win1_Enable:1; // A+B: 0=disable, 1=Enable
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/*15*/ u8 WinOBJ_Enable:1; // A+B: 0=disable, 1=Enable
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/*16*/ unsigned DisplayMode:2; // A+B: coreA(0..3) coreB(0..1) GBA(Green Swap)
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/*16*/ u8 DisplayMode:2; // A+B: coreA(0..3) coreB(0..1) GBA(Green Swap)
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// 0=off (white screen)
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// 1=on (normal BG & OBJ layers)
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// 2=VRAM display (coreA only)
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// 3=RAM display (coreA only, DMA transfers)
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/*18*/ unsigned VRAM_Block:2; // A : VRAM block (0..3=A..D)
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/*20*/ unsigned OBJ_Tile_1D_Bound:2; // A+B:
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/*22*/ unsigned OBJ_BMP_1D_Bound:1; // A :
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/*23*/ unsigned OBJ_HBlank_process:1; // A+B: OBJ processed during HBlank (GBA bit5)
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/*24*/ unsigned CharacBase_Block:3; // A : Character Base (64K step)
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/*27*/ unsigned ScreenBase_Block:3; // A : Screen Base (64K step)
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/*30*/ unsigned ExBGxPalette_Enable:1; // A+B: 0=disable, 1=Enable BG extended Palette
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/*31*/ unsigned ExOBJPalette_Enable:1; // A+B: 0=disable, 1=Enable OBJ extended Palette
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};
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/*18*/ u8 VRAM_Block:2; // A : VRAM block (0..3=A..D)
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/*20*/ u8 OBJ_Tile_1D_Bound:2; // A+B:
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/*22*/ u8 OBJ_BMP_1D_Bound:1; // A :
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/*23*/ u8 OBJ_HBlank_process:1; // A+B: OBJ processed during HBlank (GBA bit5)
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/*24*/ u8 CharacBase_Block:3; // A : Character Base (64K step)
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/*27*/ u8 ScreenBase_Block:3; // A : Screen Base (64K step)
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/*30*/ u8 ExBGxPalette_Enable:1; // A+B: 0=disable, 1=Enable BG extended Palette
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/*31*/ u8 ExOBJPalette_Enable:1; // A+B: 0=disable, 1=Enable OBJ extended Palette
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};
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typedef union
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{
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struct _DISPCNT bits;
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u32 val;
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} DISPCNT;
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} DISPCNT;
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#define BGxENABLED(cnt,num) ((num<8)? ((cnt.val>>8) & num):0)
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@ -95,27 +95,27 @@ typedef union
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struct _BGxCNT
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{
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/* 0*/ unsigned Priority:2; // 0..3=high..low
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/* 2*/ unsigned CharacBase_Block:4; // individual character base offset (n*16KB)
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/* 6*/ unsigned Mosaic_Enable:1; // 0=disable, 1=Enable mosaic
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/* 7*/ unsigned Palette_256:1; // 0=16x16, 1=1*256 palette
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/* 8*/ unsigned ScreenBase_Block:5; // individual screen base offset (text n*2KB, BMP n*16KB)
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/*13*/ unsigned PaletteSet_Wrap:1; // BG0 extended palette set 0=set0, 1=set2
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/* 0*/ u8 Priority:2; // 0..3=high..low
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/* 2*/ u8 CharacBase_Block:4; // individual character base offset (n*16KB)
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/* 6*/ u8 Mosaic_Enable:1; // 0=disable, 1=Enable mosaic
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/* 7*/ u8 Palette_256:1; // 0=16x16, 1=1*256 palette
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/* 8*/ u8 ScreenBase_Block:5; // individual screen base offset (text n*2KB, BMP n*16KB)
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/*13*/ u8 PaletteSet_Wrap:1; // BG0 extended palette set 0=set0, 1=set2
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// BG1 extended palette set 0=set1, 1=set3
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// BG2 overflow area wraparound 0=off, 1=wrap
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// BG3 overflow area wraparound 0=off, 1=wrap
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/*14*/ unsigned ScreenSize:2; // text : 256x256 512x256 256x512 512x512
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/*14*/ u8 ScreenSize:2; // text : 256x256 512x256 256x512 512x512
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// x/rot/s : 128x128 256x256 512x512 1024x1024
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// bmp : 128x128 256x256 512x256 512x512
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// large : 512x1024 1024x512 - -
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};
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};
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||||
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct _BGxCNT bits;
|
||||
u16 val;
|
||||
} BGxCNT;
|
||||
} BGxCNT;
|
||||
|
||||
/*******************************************************************************
|
||||
this structure is for background offset
|
||||
|
|
@ -124,7 +124,7 @@ typedef union
|
|||
typedef struct {
|
||||
u16 BGxHOFS;
|
||||
u16 BGxVOFS;
|
||||
} BGxOFS;
|
||||
} BGxOFS;
|
||||
|
||||
/*******************************************************************************
|
||||
this structure is for rotoscale parameters
|
||||
|
|
@ -137,7 +137,7 @@ typedef struct {
|
|||
u16 BGxPD;
|
||||
u32 BGxX;
|
||||
u32 BGxY;
|
||||
} BGxPARMS;
|
||||
} BGxPARMS;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -151,7 +151,7 @@ typedef struct {
|
|||
u16 WIN1V;
|
||||
u16 WININ;
|
||||
u16 WINOUT;
|
||||
} WINCNT;
|
||||
} WINCNT;
|
||||
|
||||
/*******************************************************************************
|
||||
this structure is for miscellanous settings
|
||||
|
|
@ -168,7 +168,7 @@ typedef struct {
|
|||
u16 unused4;
|
||||
u16 unused5;
|
||||
u16 unused6;
|
||||
} MISCCNT;
|
||||
} MISCCNT;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -177,26 +177,26 @@ typedef struct {
|
|||
|
||||
struct _DISP3DCNT
|
||||
{
|
||||
/* 0*/ unsigned EnableTexMapping:1; //
|
||||
/* 1*/ unsigned PolygonShading:1; // 0=Toon Shading, 1=Highlight Shading
|
||||
/* 2*/ unsigned EnableAlphaTest:1; // see ALPHA_TEST_REF
|
||||
/* 3*/ unsigned EnableAlphaBlending:1; // see various Alpha values
|
||||
/* 4*/ unsigned EnableAntiAliasing:1; //
|
||||
/* 5*/ unsigned EnableEdgeMarking:1; // see EDGE_COLOR
|
||||
/* 6*/ unsigned FogOnlyAlpha:1; // 0=Alpha and Color, 1=Only Alpha (see FOG_COLOR)
|
||||
/* 7*/ unsigned EnableFog:1; // Fog Master Enable
|
||||
/* 8*/ unsigned FogShiftSHR:4; // 0..10 SHR-Divider (see FOG_OFFSET)
|
||||
/*12*/ unsigned AckColorBufferUnderflow:1; // Color Buffer RDLINES Underflow (0=None, 1=Underflow/Acknowledge)
|
||||
/*13*/ unsigned AckVertexRAMOverflow:1; // Polygon/Vertex RAM Overflow (0=None, 1=Overflow/Acknowledge)
|
||||
/*14*/ unsigned RearPlaneMode:1; // 0=Blank, 1=Bitmap
|
||||
/*15*/ unsigned :17;
|
||||
};
|
||||
/* 0*/ u8 EnableTexMapping:1; //
|
||||
/* 1*/ u8 PolygonShading:1; // 0=Toon Shading, 1=Highlight Shading
|
||||
/* 2*/ u8 EnableAlphaTest:1; // see ALPHA_TEST_REF
|
||||
/* 3*/ u8 EnableAlphaBlending:1; // see various Alpha values
|
||||
/* 4*/ u8 EnableAntiAliasing:1; //
|
||||
/* 5*/ u8 EnableEdgeMarking:1; // see EDGE_COLOR
|
||||
/* 6*/ u8 FogOnlyAlpha:1; // 0=Alpha and Color, 1=Only Alpha (see FOG_COLOR)
|
||||
/* 7*/ u8 EnableFog:1; // Fog Master Enable
|
||||
/* 8*/ u8 FogShiftSHR:4; // 0..10 SHR-Divider (see FOG_OFFSET)
|
||||
/*12*/ u8 AckColorBufferUnderflow:1; // Color Buffer RDLINES Underflow (0=None, 1=Underflow/Acknowledge)
|
||||
/*13*/ u8 AckVertexRAMOverflow:1; // Polygon/Vertex RAM Overflow (0=None, 1=Overflow/Acknowledge)
|
||||
/*14*/ u8 RearPlaneMode:1; // 0=Blank, 1=Bitmap
|
||||
/*15*/ u8 :17;
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct _DISP3DCNT bits;
|
||||
u32 val;
|
||||
} DISP3DCNT;
|
||||
} DISP3DCNT;
|
||||
|
||||
/*******************************************************************************
|
||||
this structure is for capture control (core A only)
|
||||
|
|
@ -207,27 +207,27 @@ typedef union
|
|||
|
||||
struct _DISPCAPCNT
|
||||
{
|
||||
/* 0*/ unsigned BlendFactor_A:5; // 0..16 = Blending Factor for Source A
|
||||
/* 5*/ unsigned :3; //
|
||||
/* 8*/ unsigned BlendFactor_B:5; // 0..16 = Blending Factor for Source B
|
||||
/*13*/ unsigned :3; //
|
||||
/*16*/ unsigned VRAM_Write_Block:2; // 0..3 = VRAM A..D
|
||||
/*18*/ unsigned VRAM_Write_Offset:2; // n x 0x08000
|
||||
/*20*/ unsigned Capture_Size:2; // 0=128x128, 1=256x64, 2=256x128, 3=256x192 dots
|
||||
/*22*/ unsigned :2; //
|
||||
/*24*/ unsigned Source_A:1; // 0=Graphics Screen BG+3D+OBJ, 1=3D Screen
|
||||
/*25*/ unsigned Source_B:1; // 0=VRAM, 1=Main Memory Display FIFO
|
||||
/*26*/ unsigned VRAM_Read_Offset:2; // n x 0x08000
|
||||
/*28*/ unsigned :1; //
|
||||
/*29*/ unsigned Capture_Source:2; // 0=Source A, 1=Source B, 2/3=Sources A+B blended
|
||||
/*31*/ unsigned Capture_Enable:1; // 0=Disable/Ready, 1=Enable/Busy
|
||||
};
|
||||
/* 0*/ u8 BlendFactor_A:5; // 0..16 = Blending Factor for Source A
|
||||
/* 5*/ u8 :3; //
|
||||
/* 8*/ u8 BlendFactor_B:5; // 0..16 = Blending Factor for Source B
|
||||
/*13*/ u8 :3; //
|
||||
/*16*/ u8 VRAM_Write_Block:2; // 0..3 = VRAM A..D
|
||||
/*18*/ u8 VRAM_Write_Offset:2; // n x 0x08000
|
||||
/*20*/ u8 Capture_Size:2; // 0=128x128, 1=256x64, 2=256x128, 3=256x192 dots
|
||||
/*22*/ u8 :2; //
|
||||
/*24*/ u8 Source_A:1; // 0=Graphics Screen BG+3D+OBJ, 1=3D Screen
|
||||
/*25*/ u8 Source_B:1; // 0=VRAM, 1=Main Memory Display FIFO
|
||||
/*26*/ u8 VRAM_Read_Offset:2; // n x 0x08000
|
||||
/*28*/ u8 :1; //
|
||||
/*29*/ u8 Capture_Source:2; // 0=Source A, 1=Source B, 2/3=Sources A+B blended
|
||||
/*31*/ u8 Capture_Enable:1; // 0=Disable/Ready, 1=Enable/Busy
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct _DISPCAPCNT bits;
|
||||
u32 val;
|
||||
} DISPCAPCNT;
|
||||
} DISPCAPCNT;
|
||||
|
||||
|
||||
|
||||
|
|
@ -241,17 +241,17 @@ typedef union
|
|||
|
||||
struct _MASTER_BRIGHT
|
||||
{
|
||||
/* 0*/ unsigned Factor:4; // combine with (Factor / 16) of white/black
|
||||
/* 4*/ unsigned FactorEx:1; // if true use white or black
|
||||
/* 5*/ unsigned :9;
|
||||
/*14*/ unsigned Mode:2; // 0=off, 1=Lighten, 2=Darken, 3=?
|
||||
};
|
||||
|
||||
/* 0*/ u8 Factor:4; // combine with (Factor / 16) of white/black
|
||||
/* 4*/ u8 FactorEx:1; // if true use white or black
|
||||
/* 5*/ u8 :9;
|
||||
/*14*/ u8 Mode:2; // 0=off, 1=Lighten, 2=Darken, 3=?
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct _MASTER_BRIGHT bits;
|
||||
u16 val;
|
||||
} MASTER_BRIGHT;
|
||||
} MASTER_BRIGHT;
|
||||
|
||||
/*******************************************************************************
|
||||
this structure holds everything and should be mapped to
|
||||
|
|
@ -273,9 +273,26 @@ typedef struct _reg_dispx {
|
|||
DISPCAPCNT dispA_DISPCAPCNT; // 0x04000064
|
||||
u32 dispA_DISPMMEMFIFO; // 0x04000068
|
||||
MASTER_BRIGHT dispx_MASTERBRIGHT; // 0x0400x06C
|
||||
} REG_DISPx;
|
||||
|
||||
} REG_DISPx ;
|
||||
|
||||
// normally should have same addresses
|
||||
static void REG_DISPx_pack_test(GPU * gpu)
|
||||
{
|
||||
REG_DISPx * r = gpu->dispx_st;
|
||||
printf ("%08x %02x\n", r, (long)(&r->dispx_DISPCNT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispA_DISPSTAT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_VCOUNT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_BGxCNT[0]) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_BGxOFS[0]) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_BG2PARMS) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_BG3PARMS) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_WINCNT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_MISC) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispA_DISP3DCNT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispA_DISPCAPCNT) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispA_DISPMMEMFIFO) - (long)r);
|
||||
printf ("\t%02x\n", (long)(&r->dispx_MASTERBRIGHT) - (long)r);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue