core:
- fix bug in IPC FIFO (https://sourceforge.net/tracker2/?func=detail&aid=2490867&group_id=164579&atid=832291)
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mtabachenko
parent
0caab415d6
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c0cb8ee700
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@ -1,33 +1,33 @@
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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Copyright (C) 2007 shash
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This file is part of DeSmuME
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DeSmuME is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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DeSmuME is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with DeSmuME; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "FIFO.h"
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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Copyright (C) 2007 shash
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This file is part of DeSmuME
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DeSmuME is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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DeSmuME is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with DeSmuME; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "FIFO.h"
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#include <string.h>
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#include "armcpu.h"
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#include "debug.h"
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#include "mem.h"
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#include "MMU.h"
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#include "MMU.h"
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// ========================================================= IPC FIFO
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IPC_FIFO ipc_fifo[2]; // 0 - ARM9
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// 1 - ARM7
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@ -47,23 +47,24 @@ void IPC_FIFOsend(u8 proc, u32 val)
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{
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u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
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if (!(cnt_l & 0x8000)) return; // FIFO disabled
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u8 proc_remote = proc ^ 1;
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if (FIFO_IS_FULL(proc)) // FIFO error
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if (FIFO_IS_FULL(proc_remote)) // FIFO error
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{
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cnt_l |= 0x4000;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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return;
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}
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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cnt_l &= 0xFFFE; // clear send empty bit
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cnt_r &= 0xFEFF; // set recv empty bit
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ipc_fifo[proc].buf[ipc_fifo[proc].tail] = val;
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ipc_fifo[proc].tail++;
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if (ipc_fifo[proc].tail == 16)
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ipc_fifo[proc].tail = 0;
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc_remote][0x40], 0x184);
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cnt_l &= 0xFFFC; // clear send empty bit & full
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cnt_r &= 0xFCFF; // set recv empty bit & full
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ipc_fifo[proc_remote].buf[ipc_fifo[proc_remote].tail] = val;
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ipc_fifo[proc_remote].tail++;
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if (ipc_fifo[proc_remote].tail == 16)
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ipc_fifo[proc_remote].tail = 0;
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if (FIFO_IS_FULL(proc))
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if (FIFO_IS_FULL(proc_remote))
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{
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cnt_l |= 0x0002; // set send full bit
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cnt_r |= 0x0200; // set recv full bit
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@ -72,16 +73,17 @@ void IPC_FIFOsend(u8 proc, u32 val)
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//LOG("IPC%s send FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"7":"9", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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T1WriteWord(MMU.MMU_MEM[proc_remote][0x40], 0x184, cnt_r);
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MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0400) << 8 );
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MMU.reg_IF[proc_remote] |= ( (cnt_r & 0x0400) << 8 );
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}
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u32 IPC_FIFOrecv(u8 proc)
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{
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u32 val = 0;
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u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
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if (!(cnt_l & 0x8000)) return (val); // FIFO disabled
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if (!(cnt_l & 0x8000)) return (0); // FIFO disabled
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u8 proc_remote = proc ^ 1;
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if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO error
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{
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@ -90,10 +92,10 @@ u32 IPC_FIFOrecv(u8 proc)
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return (val);
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}
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
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u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc_remote][0x40], 0x184);
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cnt_l &= 0xFFFD; // clear send full bit
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cnt_r &= 0xFDFF; // set recv full bit
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cnt_l &= 0xFCFF; // clear send full bit & empty
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cnt_r &= 0xFFFC; // set recv full bit & empty
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val = ipc_fifo[proc].buf[ipc_fifo[proc].head];
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ipc_fifo[proc].head++;
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@ -101,15 +103,16 @@ u32 IPC_FIFOrecv(u8 proc)
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ipc_fifo[proc].head = 0;
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if ( ipc_fifo[proc].head == ipc_fifo[proc].tail ) // FIFO empty
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{
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cnt_l |= 0x0001;
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cnt_r |= 0x0100;
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cnt_l |= 0x0100;
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cnt_r |= 0x0001;
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}
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//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"9":"7", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
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//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, r 0x%X), head %02i, tail %02i\n", proc?"7":"9", val, cnt_l, cnt_r, ipc_fifo[proc].head, ipc_fifo[proc].tail);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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T1WriteWord(MMU.MMU_MEM[proc_remote][0x40], 0x184, cnt_r);
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MMU.reg_IF[proc^1] |= ( (cnt_r & 0x0004) << 9 );
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if ((cnt_l & 0x0100) && (cnt_l & BIT(2)) )
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MMU.reg_IF[proc_remote] |= ( 1<<17 );
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return (val);
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}
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@ -135,7 +138,7 @@ void IPC_FIFOcnt(u8 proc, u16 val)
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T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
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MMU.reg_IF[proc] |= ((cnt_l & 0x0004) << 16);
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}
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// ========================================================= GFX FIFO
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GFX_FIFO gxFIFO;
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@ -2927,7 +2927,7 @@ static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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case REG_IF :
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return MMU.reg_IF[ARMCPU_ARM9];
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case REG_IPCFIFORECV :
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return IPC_FIFOrecv(ARMCPU_ARM7);
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return IPC_FIFOrecv(ARMCPU_ARM9);
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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@ -3787,14 +3787,14 @@ static u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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/* Address is an IO register */
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switch(adr)
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{
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case REG_IME :
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case REG_IME :
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return MMU.reg_IME[ARMCPU_ARM7];
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case REG_IE :
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return MMU.reg_IE[ARMCPU_ARM7];
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case REG_IF :
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return MMU.reg_IF[ARMCPU_ARM7];
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case REG_IPCFIFORECV :
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return IPC_FIFOrecv(ARMCPU_ARM9);
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return IPC_FIFOrecv(ARMCPU_ARM7);
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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@ -39,10 +39,7 @@ extern char szRomBaseName[512];
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/* theses ones for reading in rom data */
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#define ROM_8(m, a) (((u8*)(m))[(a)])
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//#define IPCFIFO 0
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//#define MAIN_MEMORY_DISP_FIFO 2
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typedef const u32 TWaitState;
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struct MMU_struct {
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