Modified the GXSTAT register handling, this is still an ugly hack but some games (like Super Mario 64) don't freeze anymore.

This commit is contained in:
luigi__ 2008-12-04 21:58:24 +00:00
parent 5c457346db
commit bd1367a536
2 changed files with 14 additions and 5 deletions

View File

@ -229,6 +229,8 @@ u32 MMU_ARM7_WAIT32[16]={
1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1,
}; };
u32 gxIRQ = 0;
// VRAM mapping // VRAM mapping
u8 *LCDdst[10] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; u8 *LCDdst[10] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
const static u32 LCDdata[10][2]= { const static u32 LCDdata[10][2]= {
@ -774,12 +776,14 @@ u32 FASTCALL _MMU_read32(u32 adr)
// This is hacked due to the only current 3D core // This is hacked due to the only current 3D core
case 0x04000600: // Geometry Engine Status Register (R and R/W) case 0x04000600: // Geometry Engine Status Register (R and R/W)
{ {
u32 gxstat = ( 2 | /* u32 gxstat = ( 2 |
(MMU.fifos[proc].full<<24)| (MMU.fifos[proc].full<<24)|
(MMU.fifos[proc].half<<25)| (MMU.fifos[proc].half<<25)|
(MMU.fifos[proc].empty<<26)| (MMU.fifos[proc].empty<<26)|
(MMU.fifos[proc].irq<<30) (MMU.fifos[proc].irq<<30)
); );*/
u32 gxstat = (2 | (3 << 25) | (gxIRQ << 30));
return gxstat; return gxstat;
} }
@ -2258,7 +2262,8 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
case 0x04000600: // Geometry Engine Status Register (R and R/W) case 0x04000600: // Geometry Engine Status Register (R and R/W)
{ {
MMU.fifos[proc].irq = (val>>30) & 0x03; //MMU.fifos[proc].irq = (val>>30) & 0x03;
gxIRQ = ((val >> 30) & 0x3);
return; return;
} }
case REG_DISPA_WININ: case REG_DISPA_WININ:

View File

@ -41,6 +41,8 @@
NDSSystem nds; NDSSystem nds;
extern u32 gxIRQ;
static u32 static u32
calc_CRC16( u32 start, const u8 *data, int count) { calc_CRC16( u32 start, const u8 *data, int count) {
int i,j; int i,j;
@ -1549,8 +1551,10 @@ NDS_exec(s32 nb, BOOL force)
if(MMU.reg_IE[0]&(1<<21)) // IRQ21 if(MMU.reg_IE[0]&(1<<21)) // IRQ21
{ {
if (MMU.fifos[0].irq==1) NDS_makeARM9Int(21); // if (MMU.fifos[0].irq==1) NDS_makeARM9Int(21);
if (MMU.fifos[0].irq==2) NDS_makeARM9Int(21); // if (MMU.fifos[0].irq==2) NDS_makeARM9Int(21);
if (gxIRQ == 1) NDS_makeARM9Int(21);
if (gxIRQ == 2) NDS_makeARM9Int(21);
} }
if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0])) if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0]))