revert last commit. (DON'T touch it if you don't understand how it work. you reverted function which used ONLY in new gxFIFO)
This commit is contained in:
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28ff237695
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bd04d8e9bb
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@ -37,7 +37,7 @@ IPC_FIFO ipc_fifo[2]; // 0 - ARM9
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u8 FORCEINLINE IPC_FIFOgetSize(u8 proc)
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u8 FORCEINLINE IPC_FIFOgetSize(u8 proc)
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{
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{
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if (ipc_fifo[proc].head < ipc_fifo[proc].tail) return (ipc_fifo[proc].tail - ipc_fifo[proc].head);
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if (ipc_fifo[proc].head < ipc_fifo[proc].tail) return (ipc_fifo[proc].tail - ipc_fifo[proc].head);
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if (ipc_fifo[proc].head > ipc_fifo[proc].tail) return (17 - (ipc_fifo[proc].head - ipc_fifo[proc].tail));
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if (ipc_fifo[proc].head > ipc_fifo[proc].tail) return (16 - (ipc_fifo[proc].head - ipc_fifo[proc].tail));
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return 0;
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return 0;
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}
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}
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@ -67,7 +67,8 @@ void IPC_FIFOsend(u8 proc, u32 val)
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cnt_l &= 0xBFFC; // clear send empty bit & full
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cnt_l &= 0xBFFC; // clear send empty bit & full
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cnt_r &= 0xBCFF; // set recv empty bit & full
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cnt_r &= 0xBCFF; // set recv empty bit & full
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ipc_fifo[proc].buf[ipc_fifo[proc].tail++] = val;
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ipc_fifo[proc].buf[ipc_fifo[proc].tail] = val;
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ipc_fifo[proc].tail++;
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ipc_fifo[proc].size = IPC_FIFOgetSize(proc);
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ipc_fifo[proc].size = IPC_FIFOgetSize(proc);
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if (ipc_fifo[proc].tail > 15) ipc_fifo[proc].tail = 0;
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if (ipc_fifo[proc].tail > 15) ipc_fifo[proc].tail = 0;
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@ -103,14 +104,14 @@ u32 IPC_FIFOrecv(u8 proc)
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cnt_l &= 0xBCFF; // clear send full bit & empty
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cnt_l &= 0xBCFF; // clear send full bit & empty
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cnt_r &= 0xBFFC; // set recv full bit & empty
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cnt_r &= 0xBFFC; // set recv full bit & empty
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val = ipc_fifo[proc_remote].buf[ipc_fifo[proc_remote].head++];
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val = ipc_fifo[proc_remote].buf[ipc_fifo[proc_remote].head];
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ipc_fifo[proc_remote].head++;
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ipc_fifo[proc_remote].size = IPC_FIFOgetSize(proc_remote);
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if (ipc_fifo[proc_remote].head > 15) ipc_fifo[proc_remote].head = 0;
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if (ipc_fifo[proc_remote].head > 15) ipc_fifo[proc_remote].head = 0;
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//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, tail %02i) (r 0x%X, tail %02i)\n",
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//LOG("IPC%s recv FIFO 0x%08X (l 0x%X, tail %02i) (r 0x%X, tail %02i)\n",
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// proc?"7":"9", val, cnt_l, ipc_fifo[proc].tail, cnt_r, ipc_fifo[proc^1].tail);
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// proc?"7":"9", val, cnt_l, ipc_fifo[proc].tail, cnt_r, ipc_fifo[proc^1].tail);
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ipc_fifo[proc_remote].size = IPC_FIFOgetSize(proc_remote);
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if ( ipc_fifo[proc_remote].size == 0 ) // FIFO empty
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if ( ipc_fifo[proc_remote].size == 0 ) // FIFO empty
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{
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{
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cnt_l |= 0x0100;
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cnt_l |= 0x0100;
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@ -164,7 +165,9 @@ u16 FORCEINLINE GFX_FIFOgetSize()
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void GFX_PIPEclear()
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void GFX_PIPEclear()
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{
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{
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gxPIPE.head = 0;
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gxPIPE.tail = 0;
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gxPIPE.tail = 0;
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gxPIPE.size = 0;
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}
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}
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void GFX_FIFOclear()
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void GFX_FIFOclear()
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@ -185,6 +188,8 @@ void GFX_FIFOsend(u8 cmd, u32 param)
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if (gxFIFO.size == 0) // FIFO empty
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if (gxFIFO.size == 0) // FIFO empty
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{
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{
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gxstat &= 0xF000FFFF;
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gxstat |= 0x06000000;
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if (gxPIPE.size < 4) // pipe not full
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if (gxPIPE.size < 4) // pipe not full
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{
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{
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gxPIPE.cmd[gxPIPE.tail] = cmd;
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gxPIPE.cmd[gxPIPE.tail] = cmd;
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@ -201,14 +206,19 @@ void GFX_FIFOsend(u8 cmd, u32 param)
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}
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}
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}
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}
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//INFO("GFX FIFO: Send GFX 3D cmd 0x%02X to FIFO - 0x%08X (%03i/%02X)\n", cmd, param, gxFIFO.tail, gxFIFO.tail);
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if (gxstat & 0x01000000)
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{
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//INFO("ERROR: gxFIFO is full (cmd 0x%02X = 0x%08X) (prev cmd 0x%02X = 0x%08X)\n", cmd, param, gxFIFO.cmd[255], gxFIFO.param[255]);
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return; // full
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}
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gxstat &= 0xF000FFFF;
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gxstat &= 0xF000FFFF;
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//INFO("GFX FIFO: Send GFX 3D cmd 0x%02X to FIFO - 0x%08X (%03i/%02X)\n", cmd, param, gxFIFO.tail, gxFIFO.tail);
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if (gxstat & 0x01000000) // full
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{
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#ifdef USE_GEOMETRY_FIFO_EMULATION
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gxstat &= 0xF000FFFF;
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gxstat |= 0x01000000;
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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NDS_RescheduleGXFIFO();
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#endif
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//INFO("ERROR: gxFIFO is full (cmd 0x%02X = 0x%08X) (prev cmd 0x%02X = 0x%08X)\n", cmd, param, gxFIFO.cmd[255], gxFIFO.param[255]);
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return;
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}
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gxFIFO.cmd[gxFIFO.tail] = cmd;
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gxFIFO.cmd[gxFIFO.tail] = cmd;
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gxFIFO.param[gxFIFO.tail] = param;
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gxFIFO.param[gxFIFO.tail] = param;
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@ -216,7 +226,6 @@ void GFX_FIFOsend(u8 cmd, u32 param)
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gxFIFO.size = GFX_FIFOgetSize();
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gxFIFO.size = GFX_FIFOgetSize();
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if (gxFIFO.tail > 256) gxFIFO.tail = 0;
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if (gxFIFO.tail > 256) gxFIFO.tail = 0;
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#ifdef USE_GEOMETRY_FIFO_EMULATION
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#ifdef USE_GEOMETRY_FIFO_EMULATION
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gxstat |= 0x08000000; // set busy flag
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gxstat |= 0x08000000; // set busy flag
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#endif
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#endif
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@ -237,60 +246,15 @@ void GFX_FIFOsend(u8 cmd, u32 param)
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NDS_RescheduleGXFIFO();
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NDS_RescheduleGXFIFO();
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}
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}
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// this function used ONLY in new gxFIFO
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extern void execHardware_doAllDma(EDMAMode modeNum);
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extern void execHardware_doAllDma(EDMAMode modeNum);
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BOOL FORCEINLINE GFX_FIFOrecv(u8 *cmd, u32 *param)
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// this function used ONLY in new gxFIFO
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{
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u32 gxstat = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600);
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if (gxFIFO.size == 0) // empty
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{
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gxstat &= 0xF000FFFF;
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gxstat |= 0x06000000;
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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if ((gxstat & 0xC0000000)) // IRQ: empty
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{
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setIF(0, (1<<21));
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}
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return FALSE;
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}
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if (gxstat & 0x40000000) // IRQ: less half
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{
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if (gxstat & 0x02000000) setIF(0, (1<<21));
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}
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gxstat &= 0xF000FFFF;
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*cmd = gxFIFO.cmd[gxFIFO.head];
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*param = gxFIFO.param[gxFIFO.head];
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gxFIFO.head++;
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gxFIFO.size = GFX_FIFOgetSize();
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if (gxFIFO.head > 256) gxFIFO.head = 0;
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gxstat |= ((gxFIFO.size & 0x1FF) << 16);
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if (gxFIFO.size < 128)
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{
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gxstat |= 0x02000000;
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#ifdef USE_GEOMETRY_FIFO_EMULATION
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execHardware_doAllDma(EDMAMode_GXFifo);
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#endif
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}
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if (gxFIFO.tail == gxFIFO.head) // empty
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gxstat |= 0x04000000;
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else
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gxstat |= 0x08000000; // set busy flag
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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return TRUE;
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}
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BOOL GFX_PIPErecv(u8 *cmd, u32 *param)
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BOOL GFX_PIPErecv(u8 *cmd, u32 *param)
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{
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{
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u8 tmp_cmd = 0;
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u8 tmp_cmd = 0;
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u32 tmp_param = 0;
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u32 tmp_param = 0;
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u32 gxstat = 0;
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u32 gxstat = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600);
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gxstat &= 0xF7FFFFFF; // clear busy flag
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if (gxPIPE.size > 0)
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if (gxPIPE.size > 0)
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{
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{
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@ -302,39 +266,62 @@ BOOL GFX_PIPErecv(u8 *cmd, u32 *param)
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if (gxPIPE.size < 2)
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if (gxPIPE.size < 2)
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{
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{
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if (GFX_FIFOrecv(&tmp_cmd, &tmp_param))
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if (gxFIFO.size > 0)
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{
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{
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gxPIPE.cmd[gxPIPE.tail] = tmp_cmd;
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gxstat &= 0xF000FFFF;
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gxPIPE.param[gxPIPE.tail] = tmp_param;
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gxPIPE.cmd[gxPIPE.tail] = gxFIFO.cmd[gxFIFO.head];
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gxPIPE.param[gxPIPE.tail] = gxFIFO.param[gxFIFO.head];
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gxPIPE.tail++;
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gxPIPE.tail++;
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gxPIPE.size = GFX_PIPEgetSize();
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gxPIPE.size = GFX_PIPEgetSize();
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if (gxPIPE.tail > 4) gxPIPE.tail = 0;
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if (gxPIPE.tail > 4) gxPIPE.tail = 0;
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if (GFX_FIFOrecv(&tmp_cmd, &tmp_param))
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gxFIFO.head++;
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gxFIFO.size = GFX_FIFOgetSize();
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if (gxFIFO.head > 256) gxFIFO.head = 0;
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if (gxFIFO.size > 0)
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{
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{
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gxPIPE.cmd[gxPIPE.tail] = tmp_cmd;
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gxPIPE.cmd[gxPIPE.tail] = gxFIFO.cmd[gxFIFO.head];
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gxPIPE.param[gxPIPE.tail] = tmp_param;
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gxPIPE.param[gxPIPE.tail] = gxFIFO.param[gxFIFO.head];
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gxPIPE.tail++;
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gxPIPE.tail++;
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gxPIPE.size = GFX_PIPEgetSize();
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gxPIPE.size = GFX_PIPEgetSize();
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if (gxPIPE.tail > 4) gxPIPE.tail = 0;
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if (gxPIPE.tail > 4) gxPIPE.tail = 0;
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gxFIFO.head++;
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gxFIFO.size = GFX_FIFOgetSize();
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if (gxFIFO.head > 256) gxFIFO.head = 0;
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}
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}
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gxstat |= ((gxFIFO.size & 0x1FF) << 16);
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if (gxFIFO.size < 128)
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{
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gxstat |= 0x02000000;
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execHardware_doAllDma(EDMAMode_GXFifo);
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if (gxstat & 0x40000000) // IRQ: less half
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setIF(0, (1<<21));
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}
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if (gxFIFO.tail == gxFIFO.head) // empty
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gxstat |= 0x04000000;
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}
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else // FIFO empty
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{
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gxstat &= 0xF000FFFF;
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gxstat |= 0x06000000;
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}
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}
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}
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}
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if (gxPIPE.size == 0)
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if (gxPIPE.size > 0)
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{
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gxstat |= 0x08000000; // set busy flag
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gxstat = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600);
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gxstat &= 0xF7FFFFFF; // clear busy flag
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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}
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return (TRUE);
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return (TRUE);
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}
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}
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gxstat = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600);
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gxstat &= 0xF7FFFFFF; // clear busy flag
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if (gxstat & 0x80000000) // IRQ: empty
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if ((gxstat & 0x80000000)) // IRQ: empty
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setIF(0, (1<<21));
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{
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if (gxFIFO.tail == 0) setIF(0, (1<<21));
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}
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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return FALSE;
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return FALSE;
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}
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}
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@ -352,11 +339,6 @@ void GFX_FIFOcnt(u32 val)
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
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NDS_RescheduleGXFIFO();
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NDS_RescheduleGXFIFO();
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/*if (gxstat & 0xC0000000)
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{
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setIF(0, (1<<21));
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}*/
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}
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}
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// ========================================================= DISP FIFO
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// ========================================================= DISP FIFO
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@ -318,6 +318,8 @@ void gfx3d_reset()
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memset(vertlists, 0, sizeof(vertlists));
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memset(vertlists, 0, sizeof(vertlists));
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listTwiddle = 1;
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listTwiddle = 1;
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twiddleLists();
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twiddleLists();
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gfx3d.polylist = polylist;
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gfx3d.vertlist = vertlist;
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MatrixInit (mtxCurrent[0]);
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MatrixInit (mtxCurrent[0]);
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MatrixInit (mtxCurrent[1]);
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MatrixInit (mtxCurrent[1]);
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@ -1638,6 +1640,8 @@ void gfx3d_VBlankSignal()
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{
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{
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gfx3d_doFlush();
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gfx3d_doFlush();
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isSwapBuffers = false;
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isSwapBuffers = false;
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GFX_DELAY(392);
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NDS_RescheduleGXFIFO();
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}
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}
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#else
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#else
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//the 3d buffers are swapped when a vblank begins.
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//the 3d buffers are swapped when a vblank begins.
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@ -1662,12 +1666,7 @@ void gfx3d_VBlankEndSignal(bool skipFrame)
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if (!drawPending) return;
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if (!drawPending) return;
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drawPending = FALSE;
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drawPending = FALSE;
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if(skipFrame)
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if(skipFrame) return;
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{
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GFX_DELAY(392);
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NDS_RescheduleGXFIFO();
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return;
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}
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//if the null 3d core is chosen, then we need to clear out the 3d buffers to keep old data from being rendered
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//if the null 3d core is chosen, then we need to clear out the 3d buffers to keep old data from being rendered
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if(gpu3D == &gpu3DNull || !CommonSettings.showGpu.main)
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if(gpu3D == &gpu3DNull || !CommonSettings.showGpu.main)
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{
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{
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@ -1676,9 +1675,6 @@ void gfx3d_VBlankEndSignal(bool skipFrame)
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}
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}
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gpu3D->NDS_3D_Render();
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gpu3D->NDS_3D_Render();
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GFX_DELAY(392);
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NDS_RescheduleGXFIFO();
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#else
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#else
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//if we are skipping 3d frames then the 3d rendering will get held up here.
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//if we are skipping 3d frames then the 3d rendering will get held up here.
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//but, as soon as we quit skipping frames, the held-up 3d frame will render
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//but, as soon as we quit skipping frames, the held-up 3d frame will render
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