core:
- fix IRQ handler for ARM7 when use external SWI (big speedup);
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parent
54c80ae16e
commit
b1db5d2080
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@ -1074,7 +1074,7 @@ static void execdiv() {
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}
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}
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// TODO:
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// TODO:
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// NAND flash support (used in Made in Ore/WariWare D.I.Y.)
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// NAND flash support (used in Made in Ore/WarioWare D.I.Y.)
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template<int PROCNUM>
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template<int PROCNUM>
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void FASTCALL MMU_writeToGCControl(u32 val)
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void FASTCALL MMU_writeToGCControl(u32 val)
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{
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{
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@ -1146,7 +1146,9 @@ void FASTCALL MMU_writeToGCControl(u32 val)
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case 0x85:
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case 0x85:
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{
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{
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card.address = 0;
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card.address = 0;
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card.transfer_count = 0x80;
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//card.transfer_count = 0x80;
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// needs for WarioWare D.I.Y - ingame saves don't work but game don't freeze in main menu
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card.transfer_count = 0;
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}
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}
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break;
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break;
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@ -3657,8 +3659,7 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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switch(val)
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switch(val)
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{
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{
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case 0xC0: NDS_Sleep(); break;
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case 0xC0: NDS_Sleep(); break;
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// TODO: its break firmware booting? but BIG speedup with ext. SWI
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case 0x80: armcpu_Wait4IRQ(&NDS_ARM7); break;
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//case 0x80: NDS_ARM7.waitIRQ = 1; break;
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default: break;
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default: break;
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}
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}
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break;
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break;
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@ -371,6 +371,35 @@ u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode)
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return oldmode;
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return oldmode;
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}
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}
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u32 armcpu_Wait4IRQ(armcpu_t *cpu)
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{
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u32 instructAddr = cpu->instruct_adr;
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// on the first call, wirq is not set
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if(cpu->wirq)
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{
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// check wether an irq was issued
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if(!cpu->waitIRQ)
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{
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cpu->waitIRQ = 0;
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cpu->wirq = 0;
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return 1; // return execution
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}
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// otherwise, repeat this instruction
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cpu->R[15] = instructAddr;
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cpu->next_instruction = instructAddr;
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return 1;
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}
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// first run, set us into waiting state
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cpu->waitIRQ = 1;
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cpu->wirq = 1;
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// and set next instruction to repeat this
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cpu->R[15] = instructAddr;
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cpu->next_instruction = instructAddr;
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// only SWI set IME to 1
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return 1;
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}
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template<u32 PROCNUM>
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template<u32 PROCNUM>
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FORCEINLINE static u32 armcpu_prefetch()
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FORCEINLINE static u32 armcpu_prefetch()
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{
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{
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@ -554,7 +583,8 @@ BOOL armcpu_irqException(armcpu_t *armcpu)
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u32 TRAPUNDEF(armcpu_t* cpu)
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u32 TRAPUNDEF(armcpu_t* cpu)
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{
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{
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LOG("Undefined instruction: %#08X PC = %#08X \n", cpu->instruction, cpu->instruct_adr);
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INFO("ARM%c: Undefined instruction: 0x%08X (%s) PC=0x%08X\n", cpu->proc_ID?'7':'9', cpu->instruction, decodeIntruction(false, cpu->instruction), cpu->instruct_adr);
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if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
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if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
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{
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{
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armcpu_exception(&NDS_ARM9,0x04);
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armcpu_exception(&NDS_ARM9,0x04);
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@ -592,59 +622,60 @@ u32 armcpu_exec()
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//this assert is annoying. but sometimes it is handy.
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//this assert is annoying. but sometimes it is handy.
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//assert(ARMPROC.instruct_adr!=0x00000000);
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//assert(ARMPROC.instruct_adr!=0x00000000);
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//#ifdef DEVELOPER
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//#ifdef DEVELOPER
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// if ((((ARMPROC.instruct_adr & 0x0F000000) == 0x0F000000) && (PROCNUM == 0)) ||
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#if 0
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// (((ARMPROC.instruct_adr & 0x0F000000) == 0x00000000) && (PROCNUM == 1)))
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if ((((ARMPROC.instruct_adr & 0x0F000000) == 0x0F000000) && (PROCNUM == 0)) ||
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// {
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(((ARMPROC.instruct_adr & 0x0F000000) == 0x00000000) && (PROCNUM == 1)))
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// switch (ARMPROC.instruct_adr & 0xFFFF)
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{
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// {
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switch (ARMPROC.instruct_adr & 0xFFFF)
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// case 0x00000000:
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{
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// printf("BIOS%c: Reset!!!\n", PROCNUM?'7':'9');
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case 0x00000000:
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// emu_halt();
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printf("BIOS%c: Reset!!!\n", PROCNUM?'7':'9');
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// break;
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emu_halt();
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// case 0x00000004:
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break;
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// printf("BIOS%c: Undefined instruction\n", PROCNUM?'7':'9');
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case 0x00000004:
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// //emu_halt();
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printf("BIOS%c: Undefined instruction\n", PROCNUM?'7':'9');
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// break;
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//emu_halt();
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// case 0x00000008:
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break;
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// //printf("BIOS%c: SWI\n", PROCNUM?'7':'9');
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case 0x00000008:
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// break;
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//printf("BIOS%c: SWI\n", PROCNUM?'7':'9');
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// case 0x0000000C:
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break;
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// printf("BIOS%c: Prefetch Abort!!!\n", PROCNUM?'7':'9');
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case 0x0000000C:
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// //emu_halt();
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printf("BIOS%c: Prefetch Abort!!!\n", PROCNUM?'7':'9');
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// break;
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//emu_halt();
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// case 0x00000010:
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break;
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// //printf("BIOS%c: Data Abort!!!\n", PROCNUM?'7':'9');
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case 0x00000010:
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// //emu_halt();
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//printf("BIOS%c: Data Abort!!!\n", PROCNUM?'7':'9');
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// break;
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//emu_halt();
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// case 0x00000014:
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break;
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// printf("BIOS%c: Reserved!!!\n", PROCNUM?'7':'9');
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case 0x00000014:
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// break;
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printf("BIOS%c: Reserved!!!\n", PROCNUM?'7':'9');
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// case 0x00000018:
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break;
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// //printf("BIOS%c: IRQ\n", PROCNUM?'7':'9');
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case 0x00000018:
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// break;
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//printf("BIOS%c: IRQ\n", PROCNUM?'7':'9');
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// case 0x0000001C:
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break;
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// printf("BIOS%c: Fast IRQ\n", PROCNUM?'7':'9');
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case 0x0000001C:
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// break;
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printf("BIOS%c: Fast IRQ\n", PROCNUM?'7':'9');
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// }
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break;
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// }
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}
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//#endif
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}
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//
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#endif
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//#ifdef GDB_STUB
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// if (ARMPROC.stalled) {
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#ifdef GDB_STUB
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// return STALLED_CYCLE_COUNT;
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if (ARMPROC.stalled) {
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// }
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return STALLED_CYCLE_COUNT;
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//
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}
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// /* check for interrupts */
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// if (ARMPROC.irq_flag) {
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/* check for interrupts */
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// armcpu_irqException(&ARMPROC);
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if (ARMPROC.irq_flag) {
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// }
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armcpu_irqException(&ARMPROC);
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//
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}
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// cFetch = armcpu_prefetch(&ARMPROC);
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//
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cFetch = armcpu_prefetch(&ARMPROC);
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// if (ARMPROC.stalled) {
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// return MMU_fetchExecuteCycles<PROCNUM>(cExecute, cFetch);
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if (ARMPROC.stalled) {
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// }
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return MMU_fetchExecuteCycles<PROCNUM>(cExecute, cFetch);
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//#endif
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}
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#endif
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//cFetch = armcpu_prefetch(&ARMPROC);
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//cFetch = armcpu_prefetch(&ARMPROC);
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@ -253,6 +253,7 @@ BOOL armcpu_irqException(armcpu_t *armcpu);
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BOOL armcpu_flagIrq( armcpu_t *armcpu);
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BOOL armcpu_flagIrq( armcpu_t *armcpu);
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void armcpu_exception(armcpu_t *cpu, u32 number);
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void armcpu_exception(armcpu_t *cpu, u32 number);
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u32 TRAPUNDEF(armcpu_t* cpu);
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u32 TRAPUNDEF(armcpu_t* cpu);
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u32 armcpu_Wait4IRQ(armcpu_t *cpu);
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extern armcpu_t NDS_ARM7;
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extern armcpu_t NDS_ARM7;
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extern armcpu_t NDS_ARM9;
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extern armcpu_t NDS_ARM9;
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