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Merge pull request #867 from lifehackerhansol/libnds-v2 

Minor fixes for libnds v2.0.0 release
This commit is contained in:
zeromus 2024-11-14 23:54:53 -05:00 committed by GitHub
parent 1192bf6f2c ee39a36f20
commit b022181a05
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GPG Key ID: B5690EEEBB952194
2 changed files with 44 additions and 1 deletions
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29
desmume/src/MMU.cpp
View File

@ -3755,6 +3755,20 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
MMU_new.gxstat.write(8,adr,val);
break;
case REG_IPCSYNC:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180);
ipcsync &= 0xFF00;
ipcsync |= (val & 0xFF);
MMU_IPCSync(ARMCPU_ARM9, ipcsync);
}
case REG_IPCSYNC+1:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180);
ipcsync &= 0x00FF;
ipcsync |= ((val & 0xFF) << 8);
MMU_IPCSync(ARMCPU_ARM9, ipcsync);
}
case REG_AUXSPICNT:
case REG_AUXSPICNT+1:
write_auxspicnt(ARMCPU_ARM9, 8, adr & 1, val);
@ -5596,6 +5610,21 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
printf("Unsupported 8bit write to timer registers");
return;
case REG_IPCSYNC:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180);
ipcsync &= 0xFF00;
ipcsync |= (val & 0xFF);
MMU_IPCSync(ARMCPU_ARM7, ipcsync);
}
case REG_IPCSYNC+1:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180);
ipcsync &= 0x00FF;
ipcsync |= ((val & 0xFF) << 8);
MMU_IPCSync(ARMCPU_ARM7, ipcsync);
}
case REG_AUXSPIDATA:
{
//if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF; //zero 20-aug-2013 - this seems pointless

14
desmume/src/cp15.cpp
View File

@ -366,6 +366,13 @@ BOOL armcp15_moveCP2ARM(armcp15_t *armcp15, u32 * R, u8 CRn, u8 CRm, u8 opcode1,
}
}
return FALSE;
case 13:
if(opcode1 == 0 && opcode2 == 1)
{
*R = armcp15->processID;
return TRUE;
}
return FALSE;
default:
LOG("Unsupported CP15 operation : MRC\n");
return FALSE;
@ -488,6 +495,13 @@ BOOL armcp15_moveARM2CP(armcp15_t *armcp15, u32 val, u8 CRn, u8 CRm, u8 opcode1,
}
}
return FALSE;
case 13:
if(opcode1 == 0 && opcode2 == 1)
{
armcp15->processID = val;
return TRUE;
}
return FALSE;
default:
return FALSE;
}