enums - last enum value should not have a comma
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@ -80,7 +80,7 @@ enum PaletteMode
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enum OBJMode
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enum OBJMode
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{
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{
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OBJMode_Normal = 0,
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OBJMode_Normal = 0,
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OBJMode_Transparent = 1,
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OBJMode_Transparent = 1,
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OBJMode_Window = 2,
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OBJMode_Window = 2,
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OBJMode_Bitmap = 3
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OBJMode_Bitmap = 3
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};
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};
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@ -89,7 +89,7 @@ enum OBJShape
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{
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{
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OBJShape_Square = 0,
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OBJShape_Square = 0,
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OBJShape_Horizontal = 1,
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OBJShape_Horizontal = 1,
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OBJShape_Vertical = 2,
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OBJShape_Vertical = 2,
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OBJShape_Prohibited = 3
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OBJShape_Prohibited = 3
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};
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};
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@ -98,7 +98,7 @@ enum DisplayCaptureSize
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DisplayCaptureSize_128x128 = 0,
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DisplayCaptureSize_128x128 = 0,
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DisplayCaptureSize_256x64 = 1,
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DisplayCaptureSize_256x64 = 1,
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DisplayCaptureSize_256x128 = 2,
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DisplayCaptureSize_256x128 = 2,
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DisplayCaptureSize_256x192 = 3,
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DisplayCaptureSize_256x192 = 3
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};
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};
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union FragmentColor
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union FragmentColor
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@ -774,15 +774,15 @@ typedef struct
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enum ColorEffect
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enum ColorEffect
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{
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{
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ColorEffect_Disable = 0,
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ColorEffect_Disable = 0,
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ColorEffect_Blend = 1,
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ColorEffect_Blend = 1,
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ColorEffect_IncreaseBrightness = 2,
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ColorEffect_IncreaseBrightness = 2,
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ColorEffect_DecreaseBrightness = 3
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ColorEffect_DecreaseBrightness = 3
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};
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};
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enum GPUEngineID
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enum GPUEngineID
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{
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{
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GPUEngineID_Main = 0,
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GPUEngineID_Main = 0,
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GPUEngineID_Sub = 1
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GPUEngineID_Sub = 1
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};
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};
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@ -1007,7 +1007,7 @@ enum GPULayerID
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GPULayerID_BG2 = 2,
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GPULayerID_BG2 = 2,
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GPULayerID_BG3 = 3,
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GPULayerID_BG3 = 3,
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GPULayerID_OBJ = 4,
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GPULayerID_OBJ = 4,
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GPULayerID_Backdrop = 5
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GPULayerID_Backdrop = 5
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};
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};
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enum BGType
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enum BGType
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@ -1018,9 +1018,9 @@ enum BGType
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BGType_Large8bpp = 3,
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BGType_Large8bpp = 3,
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BGType_AffineExt = 4,
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BGType_AffineExt = 4,
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BGType_AffineExt_256x16 = 5,
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BGType_AffineExt_256x16 = 5,
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BGType_AffineExt_256x1 = 6,
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BGType_AffineExt_256x1 = 6,
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BGType_AffineExt_Direct = 7
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BGType_AffineExt_Direct = 7
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};
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};
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enum GPUDisplayMode
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enum GPUDisplayMode
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@ -1033,7 +1033,7 @@ enum GPUDisplayMode
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enum GPUMasterBrightMode
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enum GPUMasterBrightMode
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{
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{
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GPUMasterBrightMode_Disable = 0,
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GPUMasterBrightMode_Disable = 0,
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GPUMasterBrightMode_Up = 1,
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GPUMasterBrightMode_Up = 1,
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GPUMasterBrightMode_Down = 2,
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GPUMasterBrightMode_Down = 2,
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GPUMasterBrightMode_Reserved = 3
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GPUMasterBrightMode_Reserved = 3
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@ -1044,12 +1044,12 @@ enum GPULayerType
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{
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{
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GPULayerType_3D = 0,
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GPULayerType_3D = 0,
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GPULayerType_BG = 1,
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GPULayerType_BG = 1,
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GPULayerType_OBJ = 2
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GPULayerType_OBJ = 2
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};
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};
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enum NDSDisplayID
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enum NDSDisplayID
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{
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{
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NDSDisplayID_Main = 0,
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NDSDisplayID_Main = 0,
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NDSDisplayID_Touch = 1
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NDSDisplayID_Touch = 1
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};
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};
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@ -43,16 +43,16 @@ typedef const u8 TWaitState;
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enum EDMAMode
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enum EDMAMode
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{
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{
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EDMAMode_Immediate = 0,
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EDMAMode_Immediate = 0,
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EDMAMode_VBlank = 1,
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EDMAMode_VBlank = 1,
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EDMAMode_HBlank = 2,
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EDMAMode_HBlank = 2,
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EDMAMode_HStart = 3,
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EDMAMode_HStart = 3,
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EDMAMode_MemDisplay = 4,
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EDMAMode_MemDisplay = 4,
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EDMAMode_Card = 5,
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EDMAMode_Card = 5,
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EDMAMode_GBASlot = 6,
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EDMAMode_GBASlot = 6,
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EDMAMode_GXFifo = 7,
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EDMAMode_GXFifo = 7,
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EDMAMode7_Wifi = 8,
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EDMAMode7_Wifi = 8,
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EDMAMode7_GBASlot = 9,
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EDMAMode7_GBASlot = 9
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};
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};
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enum EDMABitWidth
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enum EDMABitWidth
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@ -65,16 +65,16 @@ enum EDMASourceUpdate
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{
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{
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EDMASourceUpdate_Increment = 0,
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EDMASourceUpdate_Increment = 0,
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EDMASourceUpdate_Decrement = 1,
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EDMASourceUpdate_Decrement = 1,
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EDMASourceUpdate_Fixed = 2,
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EDMASourceUpdate_Fixed = 2,
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EDMASourceUpdate_Invalid = 3,
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EDMASourceUpdate_Invalid = 3
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};
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};
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enum EDMADestinationUpdate
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enum EDMADestinationUpdate
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{
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{
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EDMADestinationUpdate_Increment = 0,
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EDMADestinationUpdate_Increment = 0,
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EDMADestinationUpdate_Decrement = 1,
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EDMADestinationUpdate_Decrement = 1,
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EDMADestinationUpdate_Fixed = 2,
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EDMADestinationUpdate_Fixed = 2,
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EDMADestinationUpdate_IncrementReload = 3,
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EDMADestinationUpdate_IncrementReload = 3
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};
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};
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//TODO
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//TODO
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@ -153,11 +153,11 @@ void NDS_RescheduleTimers();
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enum ENSATA_HANDSHAKE
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enum ENSATA_HANDSHAKE
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{
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{
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ENSATA_HANDSHAKE_none = 0,
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ENSATA_HANDSHAKE_none = 0,
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ENSATA_HANDSHAKE_query = 1,
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ENSATA_HANDSHAKE_query = 1,
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ENSATA_HANDSHAKE_ack = 2,
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ENSATA_HANDSHAKE_ack = 2,
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ENSATA_HANDSHAKE_confirm = 3,
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ENSATA_HANDSHAKE_confirm = 3,
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ENSATA_HANDSHAKE_complete = 4,
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ENSATA_HANDSHAKE_complete = 4
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};
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};
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enum NDS_CONSOLE_TYPE
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enum NDS_CONSOLE_TYPE
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@ -596,9 +596,9 @@ extern struct TCommonSettings {
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enum MicMode
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enum MicMode
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{
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{
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InternalNoise = 0,
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InternalNoise = 0,
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Sample = 1,
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Sample = 1,
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Random = 2,
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Random = 2,
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Physical = 3,
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Physical = 3
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} micMode;
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} micMode;
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@ -47,7 +47,7 @@ FORCEINLINE s32 spumuldiv7(s32 val, u8 multiplier) {
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enum SPUInterpolationMode
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enum SPUInterpolationMode
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{
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{
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SPUInterpolation_None = 0,
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SPUInterpolation_None = 0,
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SPUInterpolation_Linear = 1,
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SPUInterpolation_Linear = 1,
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SPUInterpolation_Cosine = 2
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SPUInterpolation_Cosine = 2
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};
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};
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@ -46,8 +46,8 @@ public:
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enum eStepMainLoopResult
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enum eStepMainLoopResult
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{
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{
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ESTEP_NOT_IMPLEMENTED = -1,
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ESTEP_NOT_IMPLEMENTED = -1,
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ESTEP_CALL_AGAIN = 0,
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ESTEP_CALL_AGAIN = 0,
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ESTEP_DONE = 1,
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ESTEP_DONE = 1
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};
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};
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virtual eStepMainLoopResult EMU_StepMainLoop(bool allowSleep, bool allowPause, int frameSkip, bool disableUser, bool disableCore) { return ESTEP_NOT_IMPLEMENTED; } // -1 frameSkip == useCurrentDefault
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virtual eStepMainLoopResult EMU_StepMainLoop(bool allowSleep, bool allowPause, int frameSkip, bool disableUser, bool disableCore) { return ESTEP_NOT_IMPLEMENTED; } // -1 frameSkip == useCurrentDefault
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virtual void EMU_PauseEmulation(bool pause) {}
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virtual void EMU_PauseEmulation(bool pause) {}
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@ -88,11 +88,11 @@ enum MatrixMode
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enum PolygonPrimitiveType
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enum PolygonPrimitiveType
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{
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{
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GFX3D_TRIANGLES = 0,
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GFX3D_TRIANGLES = 0,
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GFX3D_QUADS = 1,
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GFX3D_QUADS = 1,
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GFX3D_TRIANGLE_STRIP = 2,
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GFX3D_TRIANGLE_STRIP = 2,
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GFX3D_QUAD_STRIP = 3,
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GFX3D_QUAD_STRIP = 3,
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GFX3D_TRIANGLES_LINE = 4,
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GFX3D_TRIANGLES_LINE = 4,
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GFX3D_QUADS_LINE = 5,
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GFX3D_QUADS_LINE = 5,
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GFX3D_TRIANGLE_STRIP_LINE = 6,
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GFX3D_TRIANGLE_STRIP_LINE = 6,
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GFX3D_QUAD_STRIP_LINE = 7
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GFX3D_QUAD_STRIP_LINE = 7
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};
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};
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@ -110,7 +110,7 @@ enum PolygonMode
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enum PolygonType
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enum PolygonType
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{
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{
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POLYGON_TYPE_TRIANGLE = 3,
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POLYGON_TYPE_TRIANGLE = 3,
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POLYGON_TYPE_QUAD = 4
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POLYGON_TYPE_QUAD = 4
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};
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};
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// POLYGON ATTRIBUTES - BIT LOCATIONS
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// POLYGON ATTRIBUTES - BIT LOCATIONS
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@ -120,7 +120,7 @@ enum
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POLYGON_ATTR_ENABLE_LIGHT1_BIT = 1,
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POLYGON_ATTR_ENABLE_LIGHT1_BIT = 1,
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POLYGON_ATTR_ENABLE_LIGHT2_BIT = 2,
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POLYGON_ATTR_ENABLE_LIGHT2_BIT = 2,
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POLYGON_ATTR_ENABLE_LIGHT3_BIT = 3,
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POLYGON_ATTR_ENABLE_LIGHT3_BIT = 3,
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POLYGON_ATTR_MODE_BIT = 4, // Bits 4 - 5
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POLYGON_ATTR_MODE_BIT = 4, // Bits 4 - 5
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POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT = 6,
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POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT = 6,
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POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT = 7,
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POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT = 7,
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// Bits 8 - 10 unused
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// Bits 8 - 10 unused
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@ -129,9 +129,9 @@ enum
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POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT = 13,
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POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT = 13,
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POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT = 14,
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POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT = 14,
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POLYGON_ATTR_ENABLE_FOG_BIT = 15,
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POLYGON_ATTR_ENABLE_FOG_BIT = 15,
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POLYGON_ATTR_ALPHA_BIT = 16, // Bits 16 - 20
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POLYGON_ATTR_ALPHA_BIT = 16, // Bits 16 - 20
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// Bits 21 - 23 unused
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// Bits 21 - 23 unused
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POLYGON_ATTR_POLYGON_ID_BIT = 24, // Bits 24 - 29
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POLYGON_ATTR_POLYGON_ID_BIT = 24 // Bits 24 - 29
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// Bits 30 - 31 unused
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// Bits 30 - 31 unused
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};
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};
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@ -142,44 +142,44 @@ enum
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POLYGON_ATTR_ENABLE_LIGHT1_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT1_BIT,
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POLYGON_ATTR_ENABLE_LIGHT1_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT1_BIT,
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POLYGON_ATTR_ENABLE_LIGHT2_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT2_BIT,
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POLYGON_ATTR_ENABLE_LIGHT2_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT2_BIT,
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POLYGON_ATTR_ENABLE_LIGHT3_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT3_BIT,
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POLYGON_ATTR_ENABLE_LIGHT3_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT3_BIT,
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POLYGON_ATTR_MODE_MASK = 0x03 << POLYGON_ATTR_MODE_BIT,
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POLYGON_ATTR_MODE_MASK = 0x03 << POLYGON_ATTR_MODE_BIT,
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POLYGON_ATTR_ENABLE_BACK_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT,
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POLYGON_ATTR_ENABLE_BACK_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT,
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POLYGON_ATTR_ENABLE_FRONT_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT,
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POLYGON_ATTR_ENABLE_FRONT_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT,
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POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_MASK = 0x01 << POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_BIT,
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POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_MASK= 0x01 << POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_BIT,
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POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_MASK = 0x01 << POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_BIT,
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POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_MASK = 0x01 << POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_BIT,
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POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_MASK = 0x01 << POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT,
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POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_MASK = 0x01 << POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT,
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POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_MASK = 0x01 << POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT,
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POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_MASK = 0x01 << POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT,
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POLYGON_ATTR_ENABLE_FOG_MASK = 0x01 << POLYGON_ATTR_ENABLE_FOG_BIT,
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POLYGON_ATTR_ENABLE_FOG_MASK = 0x01 << POLYGON_ATTR_ENABLE_FOG_BIT,
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POLYGON_ATTR_ALPHA_MASK = 0x1F << POLYGON_ATTR_ALPHA_BIT,
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POLYGON_ATTR_ALPHA_MASK = 0x1F << POLYGON_ATTR_ALPHA_BIT,
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POLYGON_ATTR_POLYGON_ID_MASK = 0x3F << POLYGON_ATTR_POLYGON_ID_BIT
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POLYGON_ATTR_POLYGON_ID_MASK = 0x3F << POLYGON_ATTR_POLYGON_ID_BIT
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};
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};
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// TEXTURE PARAMETERS - BIT LOCATIONS
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// TEXTURE PARAMETERS - BIT LOCATIONS
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enum
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enum
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{
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{
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TEXTURE_PARAM_VRAM_OFFSET_BIT = 0, // Bits 0 - 15
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TEXTURE_PARAM_VRAM_OFFSET_BIT = 0, // Bits 0 - 15
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TEXTURE_PARAM_ENABLE_REPEAT_S_BIT = 16,
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TEXTURE_PARAM_ENABLE_REPEAT_S_BIT = 16,
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TEXTURE_PARAM_ENABLE_REPEAT_T_BIT = 17,
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TEXTURE_PARAM_ENABLE_REPEAT_T_BIT = 17,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT = 18,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT = 18,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT = 19,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT = 19,
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TEXTURE_PARAM_SIZE_S_BIT = 20, // Bits 20 - 22
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TEXTURE_PARAM_SIZE_S_BIT = 20, // Bits 20 - 22
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TEXTURE_PARAM_SIZE_T_BIT = 23, // Bits 23 - 25
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TEXTURE_PARAM_SIZE_T_BIT = 23, // Bits 23 - 25
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TEXTURE_PARAM_FORMAT_BIT = 26, // Bits 26 - 28
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TEXTURE_PARAM_FORMAT_BIT = 26, // Bits 26 - 28
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TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT = 29,
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TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT = 29,
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TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT = 30 // Bits 30 - 31
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TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT = 30 // Bits 30 - 31
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};
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};
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// TEXTURE PARAMETERS - BIT MASKS
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// TEXTURE PARAMETERS - BIT MASKS
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enum
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enum
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{
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{
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TEXTURE_PARAM_VRAM_OFFSET_MASK = 0xFFFF << TEXTURE_PARAM_VRAM_OFFSET_BIT,
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TEXTURE_PARAM_VRAM_OFFSET_MASK = 0xFFFF << TEXTURE_PARAM_VRAM_OFFSET_BIT,
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TEXTURE_PARAM_ENABLE_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_S_BIT,
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TEXTURE_PARAM_ENABLE_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_S_BIT,
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TEXTURE_PARAM_ENABLE_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_T_BIT,
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TEXTURE_PARAM_ENABLE_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_T_BIT,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT,
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TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT,
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TEXTURE_PARAM_SIZE_S_MASK = 0x07 << TEXTURE_PARAM_SIZE_S_BIT,
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TEXTURE_PARAM_SIZE_S_MASK = 0x07 << TEXTURE_PARAM_SIZE_S_BIT,
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TEXTURE_PARAM_SIZE_T_MASK = 0x07 << TEXTURE_PARAM_SIZE_T_BIT,
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TEXTURE_PARAM_SIZE_T_MASK = 0x07 << TEXTURE_PARAM_SIZE_T_BIT,
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TEXTURE_PARAM_FORMAT_MASK = 0x07 << TEXTURE_PARAM_FORMAT_BIT,
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TEXTURE_PARAM_FORMAT_MASK = 0x07 << TEXTURE_PARAM_FORMAT_BIT,
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TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_MASK = 0x01 << TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT,
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TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_MASK = 0x01 << TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT,
|
||||||
TEXTURE_PARAM_COORD_TRANSFORM_MODE_MASK = 0x03 << TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT
|
TEXTURE_PARAM_COORD_TRANSFORM_MODE_MASK = 0x03 << TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT
|
||||||
};
|
};
|
||||||
|
|
|
@ -29,9 +29,9 @@ enum MMU_ACCESS_TYPE
|
||||||
{
|
{
|
||||||
MMU_AT_CODE, //used for cpu prefetches
|
MMU_AT_CODE, //used for cpu prefetches
|
||||||
MMU_AT_DATA, //used for cpu read/write
|
MMU_AT_DATA, //used for cpu read/write
|
||||||
MMU_AT_GPU, //used for gpu read/write
|
MMU_AT_GPU, //used for gpu read/write
|
||||||
MMU_AT_DMA, //used for dma read/write (blocks access to TCM)
|
MMU_AT_DMA, //used for dma read/write (blocks access to TCM)
|
||||||
MMU_AT_DEBUG, //used for emulator debugging functions (bypasses some debug handling)
|
MMU_AT_DEBUG //used for emulator debugging functions (bypasses some debug handling)
|
||||||
};
|
};
|
||||||
|
|
||||||
static INLINE u8 T1ReadByte(u8* const mem, const u32 addr)
|
static INLINE u8 T1ReadByte(u8* const mem, const u32 addr)
|
||||||
|
|
|
@ -48,16 +48,16 @@ typedef struct
|
||||||
enum EMOVIEMODE
|
enum EMOVIEMODE
|
||||||
{
|
{
|
||||||
MOVIEMODE_INACTIVE = 0,
|
MOVIEMODE_INACTIVE = 0,
|
||||||
MOVIEMODE_RECORD = 1,
|
MOVIEMODE_RECORD = 1,
|
||||||
MOVIEMODE_PLAY = 2,
|
MOVIEMODE_PLAY = 2,
|
||||||
MOVIEMODE_FINISHED = 3,
|
MOVIEMODE_FINISHED = 3
|
||||||
};
|
};
|
||||||
|
|
||||||
enum EMOVIECMD
|
enum EMOVIECMD
|
||||||
{
|
{
|
||||||
MOVIECMD_MIC = 1,
|
MOVIECMD_MIC = 1,
|
||||||
MOVIECMD_RESET = 2,
|
MOVIECMD_RESET = 2,
|
||||||
MOVIECMD_LID = 4,
|
MOVIECMD_LID = 4
|
||||||
};
|
};
|
||||||
|
|
||||||
//RLDUTSBAYXWEG
|
//RLDUTSBAYXWEG
|
||||||
|
|
|
@ -96,13 +96,13 @@ typedef ISlot1Interface* TISlot1InterfaceConstructor();
|
||||||
|
|
||||||
enum NDS_SLOT1_TYPE
|
enum NDS_SLOT1_TYPE
|
||||||
{
|
{
|
||||||
NDS_SLOT1_NONE, // 0xFF - None
|
NDS_SLOT1_NONE = 0, // 0xFF - None
|
||||||
NDS_SLOT1_RETAIL_AUTO, // 0xFE - autodetect which kind of retail card to use
|
NDS_SLOT1_RETAIL_AUTO, // 0xFE - autodetect which kind of retail card to use
|
||||||
NDS_SLOT1_R4, // 0x03 - R4 flash card
|
NDS_SLOT1_R4, // 0x03 - R4 flash card
|
||||||
NDS_SLOT1_RETAIL_NAND, // 0x02 - Made in Ore/WarioWare D.I.Y.
|
NDS_SLOT1_RETAIL_NAND, // 0x02 - Made in Ore/WarioWare D.I.Y.
|
||||||
NDS_SLOT1_RETAIL_MCROM, // 0x01 - a standard MC (eeprom, flash, fram) -bearing retail card. Also supports motion, for now, because that's the way we originally coded it
|
NDS_SLOT1_RETAIL_MCROM, // 0x01 - a standard MC (eeprom, flash, fram) -bearing retail card. Also supports motion, for now, because that's the way we originally coded it
|
||||||
NDS_SLOT1_RETAIL_DEBUG, // 0x04 - for romhacking and fan-made translations
|
NDS_SLOT1_RETAIL_DEBUG, // 0x04 - for romhacking and fan-made translations
|
||||||
NDS_SLOT1_COUNT //use to count addons - MUST BE LAST!!!
|
NDS_SLOT1_COUNT //use to count addons - MUST BE LAST!!!
|
||||||
};
|
};
|
||||||
|
|
||||||
extern ISlot1Interface* slot1_device; //the current slot1 device instance
|
extern ISlot1Interface* slot1_device; //the current slot1 device instance
|
||||||
|
|
|
@ -28,9 +28,9 @@
|
||||||
|
|
||||||
enum TexCache_TexFormat
|
enum TexCache_TexFormat
|
||||||
{
|
{
|
||||||
TexFormat_None, //used when nothing yet is cached
|
TexFormat_None = 0, //used when nothing yet is cached
|
||||||
TexFormat_32bpp, //used by ogl renderer
|
TexFormat_32bpp, //used by ogl renderer
|
||||||
TexFormat_15bpp //used by rasterizer
|
TexFormat_15bpp //used by rasterizer
|
||||||
};
|
};
|
||||||
|
|
||||||
class TexCacheItem;
|
class TexCacheItem;
|
||||||
|
|
Loading…
Reference in New Issue