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enums - last enum value should not have a comma

This commit is contained in:
twinaphex 2016-08-16 08:42:39 +02:00 committed by zeromus
parent a607264086
commit aab3a7d0a6
10 changed files with 86 additions and 86 deletions
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26
desmume/src/GPU.h
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@ -80,7 +80,7 @@ enum PaletteMode
enum OBJMode
{
OBJMode_Normal = 0,
OBJMode_Transparent = 1,
OBJMode_Transparent = 1,
OBJMode_Window = 2,
OBJMode_Bitmap = 3
};
@ -89,7 +89,7 @@ enum OBJShape
{
OBJShape_Square = 0,
OBJShape_Horizontal = 1,
OBJShape_Vertical = 2,
OBJShape_Vertical = 2,
OBJShape_Prohibited = 3
};
@ -98,7 +98,7 @@ enum DisplayCaptureSize
DisplayCaptureSize_128x128 = 0,
DisplayCaptureSize_256x64 = 1,
DisplayCaptureSize_256x128 = 2,
DisplayCaptureSize_256x192 = 3,
DisplayCaptureSize_256x192 = 3
};
union FragmentColor
@ -774,15 +774,15 @@ typedef struct
enum ColorEffect
{
ColorEffect_Disable = 0,
ColorEffect_Blend = 1,
ColorEffect_Disable = 0,
ColorEffect_Blend = 1,
ColorEffect_IncreaseBrightness = 2,
ColorEffect_DecreaseBrightness = 3
};
enum GPUEngineID
{
GPUEngineID_Main = 0,
GPUEngineID_Main = 0,
GPUEngineID_Sub = 1
};
@ -1007,7 +1007,7 @@ enum GPULayerID
GPULayerID_BG2 = 2,
GPULayerID_BG3 = 3,
GPULayerID_OBJ = 4,
GPULayerID_Backdrop = 5
GPULayerID_Backdrop = 5
};
enum BGType
@ -1018,9 +1018,9 @@ enum BGType
BGType_Large8bpp = 3,
BGType_AffineExt = 4,
BGType_AffineExt_256x16 = 5,
BGType_AffineExt_256x1 = 6,
BGType_AffineExt_Direct = 7
BGType_AffineExt_256x16 = 5,
BGType_AffineExt_256x1 = 6,
BGType_AffineExt_Direct = 7
};
enum GPUDisplayMode
@ -1033,7 +1033,7 @@ enum GPUDisplayMode
enum GPUMasterBrightMode
{
GPUMasterBrightMode_Disable = 0,
GPUMasterBrightMode_Disable = 0,
GPUMasterBrightMode_Up = 1,
GPUMasterBrightMode_Down = 2,
GPUMasterBrightMode_Reserved = 3
@ -1044,12 +1044,12 @@ enum GPULayerType
{
GPULayerType_3D = 0,
GPULayerType_BG = 1,
GPULayerType_OBJ = 2
GPULayerType_OBJ = 2
};
enum NDSDisplayID
{
NDSDisplayID_Main = 0,
NDSDisplayID_Main = 0,
NDSDisplayID_Touch = 1
};

32
desmume/src/MMU.h
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@ -43,16 +43,16 @@ typedef const u8 TWaitState;
enum EDMAMode
{
EDMAMode_Immediate = 0,
EDMAMode_VBlank = 1,
EDMAMode_HBlank = 2,
EDMAMode_HStart = 3,
EDMAMode_MemDisplay = 4,
EDMAMode_Card = 5,
EDMAMode_GBASlot = 6,
EDMAMode_GXFifo = 7,
EDMAMode7_Wifi = 8,
EDMAMode7_GBASlot = 9,
EDMAMode_Immediate = 0,
EDMAMode_VBlank = 1,
EDMAMode_HBlank = 2,
EDMAMode_HStart = 3,
EDMAMode_MemDisplay = 4,
EDMAMode_Card = 5,
EDMAMode_GBASlot = 6,
EDMAMode_GXFifo = 7,
EDMAMode7_Wifi = 8,
EDMAMode7_GBASlot = 9
};
enum EDMABitWidth
@ -65,16 +65,16 @@ enum EDMASourceUpdate
{
EDMASourceUpdate_Increment = 0,
EDMASourceUpdate_Decrement = 1,
EDMASourceUpdate_Fixed = 2,
EDMASourceUpdate_Invalid = 3,
EDMASourceUpdate_Fixed = 2,
EDMASourceUpdate_Invalid = 3
};
enum EDMADestinationUpdate
{
EDMADestinationUpdate_Increment = 0,
EDMADestinationUpdate_Decrement = 1,
EDMADestinationUpdate_Fixed = 2,
EDMADestinationUpdate_IncrementReload = 3,
EDMADestinationUpdate_Increment = 0,
EDMADestinationUpdate_Decrement = 1,
EDMADestinationUpdate_Fixed = 2,
EDMADestinationUpdate_IncrementReload = 3
};
//TODO

16
desmume/src/NDSSystem.h
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@ -153,11 +153,11 @@ void NDS_RescheduleTimers();
enum ENSATA_HANDSHAKE
{
ENSATA_HANDSHAKE_none = 0,
ENSATA_HANDSHAKE_query = 1,
ENSATA_HANDSHAKE_ack = 2,
ENSATA_HANDSHAKE_confirm = 3,
ENSATA_HANDSHAKE_complete = 4,
ENSATA_HANDSHAKE_none = 0,
ENSATA_HANDSHAKE_query = 1,
ENSATA_HANDSHAKE_ack = 2,
ENSATA_HANDSHAKE_confirm = 3,
ENSATA_HANDSHAKE_complete = 4
};
enum NDS_CONSOLE_TYPE
@ -596,9 +596,9 @@ extern struct TCommonSettings {
enum MicMode
{
InternalNoise = 0,
Sample = 1,
Random = 2,
Physical = 3,
Sample = 1,
Random = 2,
Physical = 3
} micMode;

2
desmume/src/SPU.h
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@ -47,7 +47,7 @@ FORCEINLINE s32 spumuldiv7(s32 val, u8 multiplier) {
enum SPUInterpolationMode
{
SPUInterpolation_None = 0,
SPUInterpolation_None = 0,
SPUInterpolation_Linear = 1,
SPUInterpolation_Cosine = 2
};

4
desmume/src/driver.h
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@ -46,8 +46,8 @@ public:
enum eStepMainLoopResult
{
ESTEP_NOT_IMPLEMENTED = -1,
ESTEP_CALL_AGAIN = 0,
ESTEP_DONE = 1,
ESTEP_CALL_AGAIN = 0,
ESTEP_DONE = 1
};
virtual eStepMainLoopResult EMU_StepMainLoop(bool allowSleep, bool allowPause, int frameSkip, bool disableUser, bool disableCore) { return ESTEP_NOT_IMPLEMENTED; } // -1 frameSkip == useCurrentDefault
virtual void EMU_PauseEmulation(bool pause) {}

56
desmume/src/gfx3d.h
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@ -88,11 +88,11 @@ enum MatrixMode
enum PolygonPrimitiveType
{
GFX3D_TRIANGLES = 0,
GFX3D_QUADS = 1,
GFX3D_TRIANGLE_STRIP = 2,
GFX3D_QUAD_STRIP = 3,
GFX3D_TRIANGLES_LINE = 4,
GFX3D_QUADS_LINE = 5,
GFX3D_QUADS = 1,
GFX3D_TRIANGLE_STRIP = 2,
GFX3D_QUAD_STRIP = 3,
GFX3D_TRIANGLES_LINE = 4,
GFX3D_QUADS_LINE = 5,
GFX3D_TRIANGLE_STRIP_LINE = 6,
GFX3D_QUAD_STRIP_LINE = 7
};
@ -110,7 +110,7 @@ enum PolygonMode
enum PolygonType
{
POLYGON_TYPE_TRIANGLE = 3,
POLYGON_TYPE_QUAD = 4
POLYGON_TYPE_QUAD = 4
};
// POLYGON ATTRIBUTES - BIT LOCATIONS
@ -120,7 +120,7 @@ enum
POLYGON_ATTR_ENABLE_LIGHT1_BIT = 1,
POLYGON_ATTR_ENABLE_LIGHT2_BIT = 2,
POLYGON_ATTR_ENABLE_LIGHT3_BIT = 3,
POLYGON_ATTR_MODE_BIT = 4, // Bits 4 - 5
POLYGON_ATTR_MODE_BIT = 4, // Bits 4 - 5
POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT = 6,
POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT = 7,
// Bits 8 - 10 unused
@ -129,9 +129,9 @@ enum
POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT = 13,
POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT = 14,
POLYGON_ATTR_ENABLE_FOG_BIT = 15,
POLYGON_ATTR_ALPHA_BIT = 16, // Bits 16 - 20
POLYGON_ATTR_ALPHA_BIT = 16, // Bits 16 - 20
// Bits 21 - 23 unused
POLYGON_ATTR_POLYGON_ID_BIT = 24, // Bits 24 - 29
POLYGON_ATTR_POLYGON_ID_BIT = 24 // Bits 24 - 29
// Bits 30 - 31 unused
};
@ -142,44 +142,44 @@ enum
POLYGON_ATTR_ENABLE_LIGHT1_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT1_BIT,
POLYGON_ATTR_ENABLE_LIGHT2_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT2_BIT,
POLYGON_ATTR_ENABLE_LIGHT3_MASK = 0x01 << POLYGON_ATTR_ENABLE_LIGHT3_BIT,
POLYGON_ATTR_MODE_MASK = 0x03 << POLYGON_ATTR_MODE_BIT,
POLYGON_ATTR_MODE_MASK = 0x03 << POLYGON_ATTR_MODE_BIT,
POLYGON_ATTR_ENABLE_BACK_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_BACK_SURFACE_BIT,
POLYGON_ATTR_ENABLE_FRONT_SURFACE_MASK = 0x01 << POLYGON_ATTR_ENABLE_FRONT_SURFACE_BIT,
POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_MASK = 0x01 << POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_BIT,
POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_MASK= 0x01 << POLYGON_ATTR_ENABLE_ALPHA_DEPTH_WRITE_BIT,
POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_MASK = 0x01 << POLYGON_ATTR_ENABLE_RENDER_ON_FAR_PLANE_INTERSECT_BIT,
POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_MASK = 0x01 << POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT,
POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_MASK = 0x01 << POLYGON_ATTR_ENABLE_ONE_DOT_RENDER_BIT,
POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_MASK = 0x01 << POLYGON_ATTR_ENABLE_DEPTH_EQUAL_TEST_BIT,
POLYGON_ATTR_ENABLE_FOG_MASK = 0x01 << POLYGON_ATTR_ENABLE_FOG_BIT,
POLYGON_ATTR_ALPHA_MASK = 0x1F << POLYGON_ATTR_ALPHA_BIT,
POLYGON_ATTR_POLYGON_ID_MASK = 0x3F << POLYGON_ATTR_POLYGON_ID_BIT
POLYGON_ATTR_ENABLE_FOG_MASK = 0x01 << POLYGON_ATTR_ENABLE_FOG_BIT,
POLYGON_ATTR_ALPHA_MASK = 0x1F << POLYGON_ATTR_ALPHA_BIT,
POLYGON_ATTR_POLYGON_ID_MASK = 0x3F << POLYGON_ATTR_POLYGON_ID_BIT
};
// TEXTURE PARAMETERS - BIT LOCATIONS
enum
{
TEXTURE_PARAM_VRAM_OFFSET_BIT = 0, // Bits 0 - 15
TEXTURE_PARAM_ENABLE_REPEAT_S_BIT = 16,
TEXTURE_PARAM_ENABLE_REPEAT_T_BIT = 17,
TEXTURE_PARAM_VRAM_OFFSET_BIT = 0, // Bits 0 - 15
TEXTURE_PARAM_ENABLE_REPEAT_S_BIT = 16,
TEXTURE_PARAM_ENABLE_REPEAT_T_BIT = 17,
TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT = 18,
TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT = 19,
TEXTURE_PARAM_SIZE_S_BIT = 20, // Bits 20 - 22
TEXTURE_PARAM_SIZE_T_BIT = 23, // Bits 23 - 25
TEXTURE_PARAM_FORMAT_BIT = 26, // Bits 26 - 28
TEXTURE_PARAM_SIZE_S_BIT = 20, // Bits 20 - 22
TEXTURE_PARAM_SIZE_T_BIT = 23, // Bits 23 - 25
TEXTURE_PARAM_FORMAT_BIT = 26, // Bits 26 - 28
TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT = 29,
TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT = 30 // Bits 30 - 31
TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT = 30 // Bits 30 - 31
};
// TEXTURE PARAMETERS - BIT MASKS
enum
{
TEXTURE_PARAM_VRAM_OFFSET_MASK = 0xFFFF << TEXTURE_PARAM_VRAM_OFFSET_BIT,
TEXTURE_PARAM_ENABLE_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_S_BIT,
TEXTURE_PARAM_ENABLE_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_T_BIT,
TEXTURE_PARAM_VRAM_OFFSET_MASK = 0xFFFF << TEXTURE_PARAM_VRAM_OFFSET_BIT,
TEXTURE_PARAM_ENABLE_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_S_BIT,
TEXTURE_PARAM_ENABLE_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_REPEAT_T_BIT,
TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_S_BIT,
TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_MASK = 0x01 << TEXTURE_PARAM_ENABLE_MIRRORED_REPEAT_T_BIT,
TEXTURE_PARAM_SIZE_S_MASK = 0x07 << TEXTURE_PARAM_SIZE_S_BIT,
TEXTURE_PARAM_SIZE_T_MASK = 0x07 << TEXTURE_PARAM_SIZE_T_BIT,
TEXTURE_PARAM_FORMAT_MASK = 0x07 << TEXTURE_PARAM_FORMAT_BIT,
TEXTURE_PARAM_SIZE_S_MASK = 0x07 << TEXTURE_PARAM_SIZE_S_BIT,
TEXTURE_PARAM_SIZE_T_MASK = 0x07 << TEXTURE_PARAM_SIZE_T_BIT,
TEXTURE_PARAM_FORMAT_MASK = 0x07 << TEXTURE_PARAM_FORMAT_BIT,
TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_MASK = 0x01 << TEXTURE_PARAM_ENABLE_TRANSPARENT_COLOR0_BIT,
TEXTURE_PARAM_COORD_TRANSFORM_MODE_MASK = 0x03 << TEXTURE_PARAM_COORD_TRANSFORM_MODE_BIT
};

6
desmume/src/mem.h
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@ -29,9 +29,9 @@ enum MMU_ACCESS_TYPE
{
MMU_AT_CODE, //used for cpu prefetches
MMU_AT_DATA, //used for cpu read/write
MMU_AT_GPU, //used for gpu read/write
MMU_AT_DMA, //used for dma read/write (blocks access to TCM)
MMU_AT_DEBUG, //used for emulator debugging functions (bypasses some debug handling)
MMU_AT_GPU, //used for gpu read/write
MMU_AT_DMA, //used for dma read/write (blocks access to TCM)
MMU_AT_DEBUG //used for emulator debugging functions (bypasses some debug handling)
};
static INLINE u8 T1ReadByte(u8* const mem, const u32 addr)

10
desmume/src/movie.h
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@ -48,16 +48,16 @@ typedef struct
enum EMOVIEMODE
{
MOVIEMODE_INACTIVE = 0,
MOVIEMODE_RECORD = 1,
MOVIEMODE_PLAY = 2,
MOVIEMODE_FINISHED = 3,
MOVIEMODE_RECORD = 1,
MOVIEMODE_PLAY = 2,
MOVIEMODE_FINISHED = 3
};
enum EMOVIECMD
{
MOVIECMD_MIC = 1,
MOVIECMD_MIC = 1,
MOVIECMD_RESET = 2,
MOVIECMD_LID = 4,
MOVIECMD_LID = 4
};
//RLDUTSBAYXWEG

14
desmume/src/slot1.h
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@ -96,13 +96,13 @@ typedef ISlot1Interface* TISlot1InterfaceConstructor();
enum NDS_SLOT1_TYPE
{
NDS_SLOT1_NONE, // 0xFF - None
NDS_SLOT1_RETAIL_AUTO, // 0xFE - autodetect which kind of retail card to use
NDS_SLOT1_R4, // 0x03 - R4 flash card
NDS_SLOT1_RETAIL_NAND, // 0x02 - Made in Ore/WarioWare D.I.Y.
NDS_SLOT1_RETAIL_MCROM, // 0x01 - a standard MC (eeprom, flash, fram) -bearing retail card. Also supports motion, for now, because that's the way we originally coded it
NDS_SLOT1_RETAIL_DEBUG, // 0x04 - for romhacking and fan-made translations
NDS_SLOT1_COUNT //use to count addons - MUST BE LAST!!!
NDS_SLOT1_NONE = 0, // 0xFF - None
NDS_SLOT1_RETAIL_AUTO, // 0xFE - autodetect which kind of retail card to use
NDS_SLOT1_R4, // 0x03 - R4 flash card
NDS_SLOT1_RETAIL_NAND, // 0x02 - Made in Ore/WarioWare D.I.Y.
NDS_SLOT1_RETAIL_MCROM, // 0x01 - a standard MC (eeprom, flash, fram) -bearing retail card. Also supports motion, for now, because that's the way we originally coded it
NDS_SLOT1_RETAIL_DEBUG, // 0x04 - for romhacking and fan-made translations
NDS_SLOT1_COUNT //use to count addons - MUST BE LAST!!!
};
extern ISlot1Interface* slot1_device; //the current slot1 device instance

6
desmume/src/texcache.h
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@ -28,9 +28,9 @@
enum TexCache_TexFormat
{
TexFormat_None, //used when nothing yet is cached
TexFormat_32bpp, //used by ogl renderer
TexFormat_15bpp //used by rasterizer
TexFormat_None = 0, //used when nothing yet is cached
TexFormat_32bpp, //used by ogl renderer
TexFormat_15bpp //used by rasterizer
};
class TexCacheItem;