Fixed 16-bit and 32-bit accesses to the VRAM regs
Added basic support for the VRAMSTAT, WRAMCNT, WRAMSTAT and EXMEMCNT regs (writes to these regs now write the appropriate values at the other side)
This commit is contained in:
luigi__
parent
87036ecdd1
commit
a6bf874f44
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@ -102,20 +102,20 @@ void mmu_log_debug(u32 adr, u8 proc, const char *fmt, ...)
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{
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if (adr >= 0x4000000 && adr <= 0x400006C) return; // Display Engine A
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if (adr >= 0x40000B0 && adr <= 0x4000132) return; // DMA, Timers and Keypad
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if (adr >= 0x4000180 && adr <= 0x40001BA) return; // IPC/ROM
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if (adr >= 0x4000204 && adr <= 0x4000249) return; // Memory & IRQ control
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if (adr >= 0x4000280 && adr <= 0x4000304) return; // Maths
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if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
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if (adr >= 0x4100000 && adr <= 0x4100012) return; // IPC/ROM
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//if (adr >= 0x4000180 && adr <= 0x40001BA) return; // IPC/ROM
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//if (adr >= 0x4000204 && adr <= 0x4000249) return; // Memory & IRQ control
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///if (adr >= 0x4000280 && adr <= 0x4000304) return; // Maths
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//if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
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//if (adr >= 0x4100000 && adr <= 0x4100012) return; // IPC/ROM
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}
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else
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{
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if (adr >= 0x4000000 && adr <= 0x4000003) return; // ????
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//if (adr >= 0x4000000 && adr <= 0x4000003) return; // ????
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if (adr >= 0x4000004 && adr <= 0x40001C2) return; // ARM7 I/O Map
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if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
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if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
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if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
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if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
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//if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
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//if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
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//if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
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//if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
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}
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va_list list;
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@ -511,6 +511,8 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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case 2: // C
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case 3: // D Engine A, BG
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vram_map_addr = ((VRAMBankCnt >> 3) & 3) * 0x20000;
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if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
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if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
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break ;
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case 4: // E Engine A, BG
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vram_map_addr = 0x0000000;
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@ -538,6 +540,12 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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case 1: // B Engine A, OBJ
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vram_map_addr = 0x0400000 + (((VRAMBankCnt>>3)&1)*0x20000);
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break;
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case 2: // C
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
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break;
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case 3: // D
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
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break;
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case 4: // E Engine A, OBJ
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vram_map_addr = 0x0400000;
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break;
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@ -572,6 +580,8 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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int slot_index = (VRAMBankCnt >> 3) & 0x3;
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ARM9Mem.textureSlotAddr[slot_index] = LCD_addr;
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gpu3D->NDS_3D_VramReconfigureSignal();
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if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
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if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
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}
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break;
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case 4: // E
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@ -602,9 +612,11 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
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{
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case 2: // C Engine B, BG
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vram_map_addr = 0x0200000;
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
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break ;
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case 3: // D Engine B, OBJ
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vram_map_addr = 0x0600000;
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
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break ;
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case 4: // E Engine A, BG
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ARM9Mem.ExtPal[0][0] = LCD_addr;
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@ -1501,12 +1513,11 @@ static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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GPU_setBLDY_EVY(SubScreen.gpu,val) ;
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break;
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#ifdef CHECKVRAM
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case 0x4000247: // block 7
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INFO("------- MMU write 08: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
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T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x241));
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case 0x4000247:
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/* Update WRAMSTAT at the ARM7 side */
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val);
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break;
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#endif
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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case REG_VRAMCNTC:
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@ -1765,6 +1776,14 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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return;
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case REG_EXMEMCNT:
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{
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u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x204, val);
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0xFF80) | (oldval & 0x7F));
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}
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return;
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case REG_AUXSPICNT:
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val);
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AUX_SPI_CNT = val;
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@ -1821,25 +1840,20 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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return;
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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case REG_VRAMCNTC:
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case REG_VRAMCNTD:
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case REG_VRAMCNTE:
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case REG_VRAMCNTF:
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case REG_VRAMCNTG:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
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return;
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case REG_VRAMCNTG+1: // WRAM ???
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
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case REG_VRAMCNTG:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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/* Update WRAMSTAT at the ARM7 side */
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val >> 8);
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return;
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case REG_VRAMCNTH:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
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return;
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case REG_VRAMCNTI:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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return;
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case REG_IME:
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{
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@ -2294,29 +2308,22 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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return;
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case REG_VRAMCNTA:
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case REG_VRAMCNTB:
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case REG_VRAMCNTC:
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case REG_VRAMCNTD:
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case REG_VRAMCNTE:
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case REG_VRAMCNTF:
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case REG_VRAMCNTG:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+2, (val >> 16) & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+3, (val >> 24) & 0xFF);
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return;
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case REG_VRAMCNTG+1:
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case REG_VRAMCNTE:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+2, (val >> 16) & 0xFF);
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/* Update WRAMSTAT at the ARM7 side */
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, (val >> 24) & 0xFF);
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return;
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case REG_VRAMCNTH:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
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return;
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case REG_VRAMCNTI:
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MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
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return;
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case REG_IME :
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{
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@ -2950,6 +2957,13 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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/* Address is an IO register */
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switch(adr)
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{
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case REG_EXMEMCNT:
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{
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u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0x7F) | (oldval & 0xFF80));
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}
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return;
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case REG_AUXSPICNT:
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val);
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AUX_SPI_CNT = val;
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