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substantial core peformance improvements of a few FPS: remove checks for 0 parameters in operand ROR which was a big waste of time; also rearranged MMU read/write routines inlinedness and added some early outs for DTCM and main mem. The MMU read/writes are a mess and will be overhauled soon in separate checkins.

This commit is contained in:
zeromus 2009-03-03 02:01:38 +00:00
parent 91b27d48fa
commit 964e164d2a
7 changed files with 416 additions and 320 deletions
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101
desmume/src/MMU.cpp
View File

@ -67,32 +67,98 @@ static u16 FASTCALL _MMU_ARM7_read16(u32 adr);
static u32 FASTCALL _MMU_ARM7_read32(u32 adr);
u8 _MMU_read08(int PROCNUM, u32 addr) {
u8 _MMU_read08(const int PROCNUM, u32 addr) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
//Returns data from DTCM (ARM9 only)
return T1ReadByte(ARM9Mem.ARM9_DTCM, addr & 0x3FFF);
}
if ( (addr & 0x0F000000) == 0x02000000)
return T1ReadByte( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF);
if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read08(addr);
else return _MMU_ARM7_read08(addr);
}
u16 _MMU_read16(int PROCNUM, u32 addr) {
u16 _MMU_read16(const int PROCNUM, u32 addr) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
//Returns data from DTCM (ARM9 only)
return T1ReadWord(ARM9Mem.ARM9_DTCM, addr & 0x3FFF);
}
if ( (addr & 0x0F000000) == 0x02000000)
return T1ReadWord( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF);
if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read16(addr);
else return _MMU_ARM7_read16(addr);
}
u32 _MMU_read32(int PROCNUM, u32 addr) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
//Returns data from DTCM (ARM9 only)
return T1ReadLong(ARM9Mem.ARM9_DTCM, addr & 0x3FFF);
}
if ( (addr & 0x0F000000) == 0x02000000)
return T1ReadLong( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF);
if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read32(addr);
else return _MMU_ARM7_read32(addr);
}
void _MMU_write08(int PROCNUM, u32 addr, u8 val) {
void _MMU_write08(const int PROCNUM, u32 addr, u8 val) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
T1WriteByte(ARM9Mem.ARM9_DTCM, addr & 0x3FFF, val);
return;
}
if ( (addr & 0x0F000000) == 0x02000000) {
T1WriteByte( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF, val);
return;
}
if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write08(addr,val);
else _MMU_ARM7_write08(addr,val);
}
void _MMU_write16(int PROCNUM, u32 addr, u16 val) {
void _MMU_write16(const int PROCNUM, u32 addr, u16 val) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
T1WriteWord(ARM9Mem.ARM9_DTCM, addr & 0x3FFF, val);
return;
}
if ( (addr & 0x0F000000) == 0x02000000) {
T1WriteWord( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF, val);
return;
}
if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write16(addr,val);
else _MMU_ARM7_write16(addr,val);
}
void _MMU_write32(int PROCNUM, u32 addr, u32 val) {
void _MMU_write32(const int PROCNUM, u32 addr, u32 val) {
if(PROCNUM==ARMCPU_ARM9)
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
{
T1WriteLong(ARM9Mem.ARM9_DTCM, addr & 0x3FFF, val);
return;
}
if ( (addr & 0x0F000000) == 0x02000000) {
T1WriteLong( ARM9Mem.MAIN_MEM, addr & 0x3FFFFF, val);
return;
}
if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write32(addr,val);
else _MMU_ARM7_write32(addr,val);
}
@ -274,7 +340,7 @@ u32 MMU_struct::MMU_MASK[2][256] = {
{
/* 0X*/ DUP16(0x00007FFF),
/* 1X*/ //DUP16(0x00007FFF)
/* 1X*/ DUP16(0x00000003),
/* 1X*/ DUP16(0x00000003),
/* 2X*/ DUP16(0x003FFFFF),
/* 3X*/ DUP16(0x00007FFF),
/* 4X*/ DUP16(0x00FFFFFF),
@ -423,7 +489,7 @@ void MMU_clearMem()
memset(ARM9Mem.ARM9_OAM, 0, 0x0800);
memset(ARM9Mem.ARM9_REG, 0, 0x01000000);
memset(ARM9Mem.ARM9_VMEM, 0, 0x0800);
memset(ARM9Mem.MAIN_MEM, 0, 0x400000);
memset(ARM9Mem.MAIN_MEM, 0, sizeof(ARM9Mem.MAIN_MEM));
memset(ARM9Mem.blank_memory, 0, 0x020000);
@ -2347,12 +2413,24 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
return ;
}
#endif
#ifdef EARLY_MEMORY_ACCESS
if ( (adr & 0x0F000000) == 0x02000000) {
T1WriteLong( ARM9Mem.MAIN_MEM, adr & 0x3FFFFF, val);
return;
}
#endif
if(adr<0x02000000)
{
T1WriteLong(ARM9Mem.ARM9_ITCM, adr&0x7FFF, val);
return ;
}
if(adr>=0x02400000 && adr<0x03000000) {
//int zzz=9;
}
#ifdef EXPERIMENTAL_GBASLOT
if ( (adr >= 0x08000000) && (adr < 0x0A000000) )
{
@ -2988,6 +3066,15 @@ static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
}
#endif
#ifdef EARLY_MEMORY_ACCESS
if ( (adr & 0x0F000000) == 0x02000000)
return T1ReadLong( ARM9Mem.MAIN_MEM, adr & 0x3FFFFF);
#endif
if(adr>=0x02400000 && adr<0x03000000) {
//int zzz=9;
}
if(adr<0x02000000)
return T1ReadLong(ARM9Mem.ARM9_ITCM, adr&0x7FFF);

16
desmume/src/MMU.h
View File

@ -182,12 +182,16 @@ template<int PROCNUM> void _MMU_write08(u32 addr, u8 val);
template<int PROCNUM> void _MMU_write16(u32 addr, u16 val);
template<int PROCNUM> void _MMU_write32(u32 addr, u32 val);
u8 _MMU_read08(int PROCNUM, u32 addr);
u16 _MMU_read16(int PROCNUM, u32 addr);
u32 _MMU_read32(int PROCNUM, u32 addr);
void _MMU_write08(int PROCNUM, u32 addr, u8 val);
void _MMU_write16(int PROCNUM, u32 addr, u16 val);
void _MMU_write32(int PROCNUM, u32 addr, u32 val);
u8 FASTCALL arm9_read8( void *data, u32 adr);
u16 FASTCALL arm9_read16( void *data, u32 adr);
u32 FASTCALL arm9_read32( void *data, u32 adr);
FORCEINLINE extern u8 _MMU_read08(const int PROCNUM, u32 addr);
FORCEINLINE extern u16 _MMU_read16(const int PROCNUM, u32 addr);
FORCEINLINE extern u32 _MMU_read32(const int PROCNUM, u32 addr);
FORCEINLINE extern void _MMU_write08(const int PROCNUM, u32 addr, u8 val);
FORCEINLINE extern void _MMU_write16(const int PROCNUM, u32 addr, u16 val);
FORCEINLINE extern void _MMU_write32(const int PROCNUM, u32 addr, u32 val);
#ifdef MMU_ENABLE_ACL
void FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val);

98
desmume/src/arm_instructions.cpp
View File

@ -3751,8 +3751,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF()
u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3772,8 +3771,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF()
u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3798,8 +3796,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3824,8 +3821,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3850,8 +3846,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3876,8 +3871,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3902,8 +3896,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3928,8 +3921,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3954,8 +3946,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -3980,8 +3971,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4003,8 +3993,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND()
u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4027,8 +4016,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND()
u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4056,8 +4044,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4085,8 +4072,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4114,8 +4100,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4143,8 +4128,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4172,8 +4156,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4201,8 +4184,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4230,8 +4212,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] + shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4259,8 +4240,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND()
adr = cpu->R[REG_POS(i,16)] - shift_op;
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4283,8 +4263,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND()
u32 adr = cpu->R[REG_POS(i,16)];
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4309,8 +4288,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2()
u32 adr = cpu->R[REG_POS(i,16)];
u32 val = READ32(cpu->mem_if->data, adr);
u32 old;
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4338,8 +4316,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND()
u32 adr = cpu->R[REG_POS(i,16)];
u32 val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4366,8 +4343,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4394,8 +4370,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4422,8 +4397,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4450,8 +4424,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4478,8 +4451,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4506,8 +4478,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4534,8 +4505,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -4562,8 +4532,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND()
adr = cpu->R[REG_POS(i,16)];
val = READ32(cpu->mem_if->data, adr);
if(adr&3)
val = ROR(val, 8*(adr&3));
val = ROR(val, 8*(adr&3));
if(REG_POS(i,12)==15)
{
@ -7779,8 +7748,9 @@ TEMPLATE static u32 FASTCALL OP_SWI()
//----------------BKPT-------------------------
TEMPLATE static u32 FASTCALL OP_BKPT()
{
LOG("Stopped (OP_BKPT)\n");
TRAPUNDEF();
/*LOG("Stopped (OP_BKPT)\n");
TRAPUNDEF();*/
return 4;
}
//----------------CDP-----------------------

2
desmume/src/saves.cpp
View File

@ -131,7 +131,7 @@ SFORMAT SF_ARM9[]={
SFORMAT SF_MEM[]={
{ "ITCM", 1, 0x8000, ARM9Mem.ARM9_ITCM},
{ "DTCM", 1, 0x4000, ARM9Mem.ARM9_DTCM},
{ "WRAM", 1, 0x400000, ARM9Mem.MAIN_MEM},
{ "WRAM", 1, sizeof(ARM9Mem.MAIN_MEM), ARM9Mem.MAIN_MEM},
//NOTE - this is not as large as the allocated memory.
//the memory is overlarge due to the way our memory map system is setup

27
desmume/src/windows/main.cpp
View File

@ -241,8 +241,8 @@ struct NDS_fw_config_data win_fw_config;
};*/
LRESULT CALLBACK GFX3DSettingsDlgProc(HWND hw, UINT msg, WPARAM wp, LPARAM lp);
LRESULT CALLBACK SoundSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam,
LPARAM lParam);
LRESULT CALLBACK SoundSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam);
LRESULT CALLBACK EmulationSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam);
struct configured_features {
u16 arm9_gdb_port;
@ -2023,7 +2023,8 @@ enum CONFIGSCREEN
CONFIGSCREEN_INPUT,
CONFIGSCREEN_HOTKEY,
CONFIGSCREEN_FIRMWARE,
CONFIGSCREEN_SOUND
CONFIGSCREEN_SOUND,
CONFIGSCREEN_EMULATION
};
void RunConfig(CONFIGSCREEN which)
@ -2050,6 +2051,9 @@ void RunConfig(CONFIGSCREEN which)
case CONFIGSCREEN_SOUND:
DialogBox(hAppInst, MAKEINTRESOURCE(IDD_SOUNDSETTINGS), hwnd, (DLGPROC)SoundSettingsDlgProc);
break;
case CONFIGSCREEN_EMULATION:
DialogBox(hAppInst, MAKEINTRESOURCE(IDD_EMULATIONSETTINGS), hwnd, (DLGPROC)EmulationSettingsDlgProc);
break;
}
if (tpaused)
@ -2423,6 +2427,9 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
case IDM_SOUNDSETTINGS:
RunConfig(CONFIGSCREEN_SOUND);
return 0;
case IDM_EMULATIONSETTINGS:
RunConfig(CONFIGSCREEN_EMULATION);
return 0;
case IDM_GAME_INFO:
{
@ -2932,8 +2939,18 @@ LRESULT CALLBACK GFX3DSettingsDlgProc(HWND hw, UINT msg, WPARAM wp, LPARAM lp)
return FALSE;
}
LRESULT CALLBACK SoundSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam,
LPARAM lParam)
LRESULT CALLBACK EmulationSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam)
{
switch(uMsg)
{
case WM_INITDIALOG:
break;
}
return FALSE;
}
LRESULT CALLBACK SoundSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam)
{
static UINT_PTR timerid=0;
switch (uMsg)

3
desmume/src/windows/resource.h
View File

@ -162,10 +162,12 @@
#define IDC_PROP1 909
#define IDD_BGMAP_VIEWER 911
#define IDB_BGTILES 913
#define IDD_EMULATIONSETTINGS 916
#define IDC_BGMAP_SEL 1000
#define IDC_EDIT03 1000
#define IDC_SOUNDCORECB 1000
#define IDC_BGMAP_BGXCNT 1001
#define IDC_CHECKBOX_DEBUGGERMODE 1001
#define IDC_EDIT01 1001
#define IDC_SOUNDBUFFERET 1001
#define IDC_EDIT05 1002
@ -376,6 +378,7 @@
#define IDM_SCREENSEP_BORDER 40001
#define IDM_SCREENSEP_NDSGAP 40002
#define IDM_ABOUT 40003
#define IDM_EMULATIONSETTINGS 40004
#define ID_VIEW_FRAMECOUNTER 40009
#define ID_VIEW_DISPLAYFPS 40010
#define IDM_FILE_RECORDAVI 40015

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desmume/src/windows/resources.rc
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