Whitespace cleanup, no functional changes.
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5ed65db952
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9575c907a7
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@ -461,7 +461,7 @@ void NDS_Reset( void)
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src = header->ARM7src;
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dst = header->ARM7cpy;
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for(i = 0; i < (header->ARM7binSize>>2); ++i)
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{
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MMU_write32(1, dst, T1ReadLong(MMU.CART_ROM, src));
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@ -469,10 +469,8 @@ void NDS_Reset( void)
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src += 4;
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}
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armcpu_init(&NDS_ARM7, header->ARM7exe);
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armcpu_init(&NDS_ARM9, header->ARM9exe);
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nds.ARM9Cycle = 0;
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nds.ARM7Cycle = 0;
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nds.cycles = 0;
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@ -499,53 +497,50 @@ void NDS_Reset( void)
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int fw_index;
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if ( copy_firmware_user_data( temp_buffer, MMU.fw.data)) {
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for ( fw_index = 0; fw_index < NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT; fw_index++) {
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for ( fw_index = 0; fw_index < NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT; fw_index++)
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MMU_write8( 0, 0x027FFC80 + fw_index, temp_buffer[fw_index]);
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}
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}
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}
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// Copy the whole header to Main RAM 0x27FFE00 on startup.
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// Reference: http://nocash.emubase.de/gbatek.htm#dscartridgeheader
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for (i = 0; i < ((0x170+0x90)/4); i++)
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{
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MMU_write32 (0, 0x027FFE00+i*4, LE_TO_LOCAL_32(((u32*)MMU.CART_ROM)[i]));
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}
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// Copy the whole header to Main RAM 0x27FFE00 on startup.
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// Reference: http://nocash.emubase.de/gbatek.htm#dscartridgeheader
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for (i = 0; i < ((0x170+0x90)/4); i++) {
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MMU_write32 (0, 0x027FFE00+i*4, LE_TO_LOCAL_32(((u32*)MMU.CART_ROM)[i]));
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}
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MainScreen.offset = 0;
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SubScreen.offset = 192;
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//MMU_write32(0, 0x02007FFC, 0xE92D4030);
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//ARM7 BIOS IRQ HANDLER
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MMU_write32(1, 0x00, 0xE25EF002);
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MMU_write32(1, 0x04, 0xEAFFFFFE);
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MMU_write32(1, 0x18, 0xEA000000);
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MMU_write32(1, 0x20, 0xE92D500F);
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MMU_write32(1, 0x24, 0xE3A00301);
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MMU_write32(1, 0x28, 0xE28FE000);
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MMU_write32(1, 0x2C, 0xE510F004);
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MMU_write32(1, 0x30, 0xE8BD500F);
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MMU_write32(1, 0x34, 0xE25EF004);
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//ARM9 BIOS IRQ HANDLER
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MMU_write32(0, 0xFFFF0018, 0xEA000000);
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MMU_write32(0, 0xFFFF0020, 0xE92D500F);
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MMU_write32(0, 0xFFFF0024, 0xEE190F11);
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MMU_write32(0, 0xFFFF0028, 0xE1A00620);
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MMU_write32(0, 0xFFFF002C, 0xE1A00600);
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MMU_write32(0, 0xFFFF0030, 0xE2800C40);
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MMU_write32(0, 0xFFFF0034, 0xE28FE000);
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MMU_write32(0, 0xFFFF0038, 0xE510F004);
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MMU_write32(0, 0xFFFF003C, 0xE8BD500F);
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MMU_write32(0, 0xFFFF0040, 0xE25EF004);
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MMU_write32(0, 0x0000004, 0xE3A0010E);
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MMU_write32(0, 0x0000008, 0xE3A01020);
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// MMU_write32(0, 0x000000C, 0xE1B02110);
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MMU_write32(0, 0x000000C, 0xE1B02040);
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MMU_write32(0, 0x0000010, 0xE3B02020);
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// MMU_write32(0, 0x0000010, 0xE2100202);
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//ARM7 BIOS IRQ HANDLER
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MMU_write32(1, 0x00, 0xE25EF002);
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MMU_write32(1, 0x04, 0xEAFFFFFE);
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MMU_write32(1, 0x18, 0xEA000000);
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MMU_write32(1, 0x20, 0xE92D500F);
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MMU_write32(1, 0x24, 0xE3A00301);
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MMU_write32(1, 0x28, 0xE28FE000);
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MMU_write32(1, 0x2C, 0xE510F004);
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MMU_write32(1, 0x30, 0xE8BD500F);
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MMU_write32(1, 0x34, 0xE25EF004);
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//ARM9 BIOS IRQ HANDLER
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MMU_write32(0, 0xFFFF0018, 0xEA000000);
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MMU_write32(0, 0xFFFF0020, 0xE92D500F);
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MMU_write32(0, 0xFFFF0024, 0xEE190F11);
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MMU_write32(0, 0xFFFF0028, 0xE1A00620);
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MMU_write32(0, 0xFFFF002C, 0xE1A00600);
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MMU_write32(0, 0xFFFF0030, 0xE2800C40);
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MMU_write32(0, 0xFFFF0034, 0xE28FE000);
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MMU_write32(0, 0xFFFF0038, 0xE510F004);
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MMU_write32(0, 0xFFFF003C, 0xE8BD500F);
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MMU_write32(0, 0xFFFF0040, 0xE25EF004);
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MMU_write32(0, 0x0000004, 0xE3A0010E);
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MMU_write32(0, 0x0000008, 0xE3A01020);
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// MMU_write32(0, 0x000000C, 0xE1B02110);
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MMU_write32(0, 0x000000C, 0xE1B02040);
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MMU_write32(0, 0x0000010, 0xE3B02020);
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// MMU_write32(0, 0x0000010, 0xE2100202);
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delete header;
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