GFX3D: Fix clear color on big-endian systems. (Regression from commit 97848fc.)
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dcd1072800
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@ -3665,22 +3665,22 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM9>(3,val); break;
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case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM9>(3,val); break;
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case eng_3D_CLEAR_COLOR:
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case eng_3D_CLEAR_COLOR:
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HostWriteByte(MMU.ARM9_REG, 0x0350, val);
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T1WriteByte(MMU.ARM9_REG, 0x0350, val);
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gfx3d_glClearColor<u8>(0, val);
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gfx3d_glClearColor<u8>(0, val);
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return;
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return;
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case eng_3D_CLEAR_COLOR+1:
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case eng_3D_CLEAR_COLOR+1:
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HostWriteByte(MMU.ARM9_REG, 0x0351, val);
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T1WriteByte(MMU.ARM9_REG, 0x0351, val);
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gfx3d_glClearColor<u8>(1, val);
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gfx3d_glClearColor<u8>(1, val);
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return;
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return;
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case eng_3D_CLEAR_COLOR+2:
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case eng_3D_CLEAR_COLOR+2:
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HostWriteByte(MMU.ARM9_REG, 0x0352, val);
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T1WriteByte(MMU.ARM9_REG, 0x0352, val);
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gfx3d_glClearColor<u8>(2, val);
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gfx3d_glClearColor<u8>(2, val);
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return;
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return;
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case eng_3D_CLEAR_COLOR+3:
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case eng_3D_CLEAR_COLOR+3:
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HostWriteByte(MMU.ARM9_REG, 0x0353, val);
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T1WriteByte(MMU.ARM9_REG, 0x0353, val);
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gfx3d_glClearColor<u8>(3, val);
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gfx3d_glClearColor<u8>(3, val);
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return;
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return;
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@ -2809,7 +2809,27 @@ void gfx3d_glFogOffset(const u32 v)
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template <typename T>
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template <typename T>
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void gfx3d_glClearColor(const u8 offset, const T v)
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void gfx3d_glClearColor(const u8 offset, const T v)
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{
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{
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#ifndef MSB_FIRST
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((T *)&gfx3d.pendingState.clearColor)[offset >> (sizeof(T) >> 1)] = v;
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((T *)&gfx3d.pendingState.clearColor)[offset >> (sizeof(T) >> 1)] = v;
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#else
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switch (sizeof(T))
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{
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case 1:
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((T *)&gfx3d.pendingState.clearColor)[offset >> (sizeof(T) >> 1)] = v;
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break;
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case 2:
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((T *)&gfx3d.pendingState.clearColor)[offset >> (sizeof(T) >> 1)] = LE_TO_LOCAL_16(v);
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break;
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case 4:
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((T *)&gfx3d.pendingState.clearColor)[offset >> (sizeof(T) >> 1)] = LE_TO_LOCAL_32(v);
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break;
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default:
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break;
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}
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#endif
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}
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}
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template void gfx3d_glClearColor< u8>(const u8 offset, const u8 v);
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template void gfx3d_glClearColor< u8>(const u8 offset, const u8 v);
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