parent
d6b75e99ac
commit
8c4d4bb3a1
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@ -403,8 +403,8 @@ TEMPLATE static u32 FASTCALL OP_CMP_SPE(const u32 i)
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cpu->CPSR.bits.N = BIT31(tmp);
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cpu->CPSR.bits.N = BIT31(tmp);
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cpu->CPSR.bits.Z = tmp == 0;
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cpu->CPSR.bits.Z = tmp == 0;
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cpu->CPSR.bits.C = !BorrowFrom(cpu->R[Rn], cpu->R[REG_NUM(i, 3)]);
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cpu->CPSR.bits.C = !BorrowFrom(cpu->R[Rn], cpu->R[REG_POS(i, 3)]);
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cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[Rn], cpu->R[REG_NUM(i, 3)]);
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cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[Rn], cpu->R[REG_POS(i, 3)]);
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return 1;
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return 1;
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}
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}
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@ -555,13 +555,11 @@ TEMPLATE static u32 FASTCALL OP_NEG(const u32 i)
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TEMPLATE static u32 FASTCALL OP_CMN(const u32 i)
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TEMPLATE static u32 FASTCALL OP_CMN(const u32 i)
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{
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{
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u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
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u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
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//emu_halt();
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//log::ajouter("OP_CMN THUMB");
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cpu->CPSR.bits.N = BIT31(tmp);
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cpu->CPSR.bits.N = BIT31(tmp);
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cpu->CPSR.bits.Z = tmp == 0;
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cpu->CPSR.bits.Z = tmp == 0;
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cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)], tmp);
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cpu->CPSR.bits.C = CarryFrom(cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
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cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)], tmp);
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cpu->CPSR.bits.V = OverflowFromADD(tmp, cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
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return 1;
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return 1;
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}
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}
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@ -1149,9 +1147,9 @@ TEMPLATE static u32 FASTCALL OP_BLX_THUMB(const u32 i)
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u32 Rm = cpu->R[REG_POS(i, 3)];
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u32 Rm = cpu->R[REG_POS(i, 3)];
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cpu->CPSR.bits.T = BIT0(Rm);
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cpu->CPSR.bits.T = BIT0(Rm);
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cpu->R[14] = cpu->next_instruction | 1;
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//cpu->R[15] = (Rm & (0xFFFFFFFC|(1<<cpu->CPSR.bits.T)));
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//cpu->R[15] = (Rm & (0xFFFFFFFC|(1<<cpu->CPSR.bits.T)));
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cpu->R[15] = (Rm & (0xFFFFFFFC|(1<<cpu->CPSR.bits.T)));
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cpu->R[15] = Rm & 0xFFFFFFFE;
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cpu->R[14] = cpu->next_instruction | 1;
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cpu->next_instruction = cpu->R[15];
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cpu->next_instruction = cpu->R[15];
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return 4;
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return 4;
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