More warnings fixes by riccardom (patch 2157019)
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@ -284,8 +284,6 @@ u32 DMADst[2][4] = {{0, 0, 0, 0}, {0, 0, 0, 0}};
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void MMU_clearMem()
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{
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int i;
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memset(ARM9Mem.ARM9_ABG, 0, 0x080000);
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memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000);
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memset(ARM9Mem.ARM9_BBG, 0, 0x020000);
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@ -349,7 +347,7 @@ void MMU_clearMem()
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/* the VRAM blocks keep their content even when not blended in */
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/* to ensure that we write the content back to the LCD ram */
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/* FIXME: VRAM Bank E,F,G,H,I missing */
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void MMU_VRAMWriteBackToLCD(u8 block)
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static void MMU_VRAMWriteBackToLCD(u8 block)
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{
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u8 *destination;
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u8 *source;
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@ -482,7 +480,7 @@ void MMU_VRAMWriteBackToLCD(u8 block)
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memset(source,0,size) ;
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}
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void MMU_VRAMReloadFromLCD(u8 block,u8 VRAMBankCnt)
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static void MMU_VRAMReloadFromLCD(u8 block,u8 VRAMBankCnt)
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{
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u8 *destination;
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u8 *source;
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@ -951,7 +949,7 @@ void FASTCALL _MMU_write8(u32 adr, u8 val)
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}
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}
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if (adr & 0xFF800000 == 0x04800000)
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if ((adr & 0xFF800000) == 0x04800000)
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{
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/* is wifi hardware, dont intermix with regular hardware registers */
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/* FIXME handle 8 bit writes */
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@ -1563,7 +1561,7 @@ void FASTCALL _MMU_write16(u32 adr, u16 val)
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break;
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case 1 : /* firmware memory device */
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if(spicnt & 0x3 != 0) /* check SPI baudrate (must be 4mhz) */
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if((spicnt & 0x3) != 0) /* check SPI baudrate (must be 4mhz) */
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{
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T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);
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break;
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@ -2021,7 +2019,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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}
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}
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if (adr & 0xFF800000 == 0x04800000) {
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if ((adr & 0xFF800000) == 0x04800000) {
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/* access to non regular hw registers */
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/* return to not overwrite valid data */
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return ;
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@ -2904,7 +2902,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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return;
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case REG_GCROMCTRL :
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{
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int i;
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unsigned int i;
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if(MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB7)
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{
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@ -132,7 +132,6 @@ struct armcpu_memory_iface {
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};
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static void mmu_select_savetype(int type, int *bmemtype, u32 *bmemsize) {
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if (type<0 || type > 5) return;
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*bmemtype=save_types[type][0];
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