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Added support for 16-bit and 32-bit read/writes to the RTC reg, 

and fixed the little-endian commands.
With these fixes, the SPP menu background has now the right colour depending on the time (formerly it was always night blue).
This commit is contained in:
luigi__ 2009-02-14 22:04:24 +00:00
parent fc6cbdf03d
commit 7ad6fc5257
3 changed files with 38 additions and 16 deletions
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19
desmume/src/MMU.cpp
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@ -3015,7 +3015,7 @@ static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]); adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
// this is hack // this is hack
gxstat |= 0x00000002; //gxstat |= 0x00000002;
return gxstat; return gxstat;
} }
#endif #endif
@ -3234,6 +3234,10 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
/* Address is an IO register */ /* Address is an IO register */
switch(adr) switch(adr)
{ {
case REG_RTC:
rtcWrite(val);
break;
case REG_EXMEMCNT: case REG_EXMEMCNT:
{ {
u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204); u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
@ -3624,6 +3628,7 @@ static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
return; return;
} }
#endif #endif
#ifdef EXPERIMENTAL_WIFI #ifdef EXPERIMENTAL_WIFI
@ -3648,6 +3653,10 @@ static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
{ {
switch(adr) switch(adr)
{ {
case REG_RTC:
rtcWrite((u16)val);
break;
case REG_IME : case REG_IME :
{ {
u32 old_val = MMU.reg_IME[ARMCPU_ARM7]; u32 old_val = MMU.reg_IME[ARMCPU_ARM7];
@ -3884,7 +3893,7 @@ static u8 FASTCALL _MMU_ARM7_read08(u32 adr)
return (unsigned char)cflash_read(adr); return (unsigned char)cflash_read(adr);
#endif #endif
if (adr == REG_RTC) return rtcRead(); if (adr == REG_RTC) return (u8)rtcRead();
#ifdef _MMU_DEBUG #ifdef _MMU_DEBUG
mmu_log_debug_ARM7(adr, "(read08) %0x%X", mmu_log_debug_ARM7(adr, "(read08) %0x%X",
@ -3918,6 +3927,9 @@ static u16 FASTCALL _MMU_ARM7_read16(u32 adr)
/* Address is an IO register */ /* Address is an IO register */
switch(adr) switch(adr)
{ {
case REG_RTC:
return rtcRead();
case REG_IME : case REG_IME :
return (u16)MMU.reg_IME[ARMCPU_ARM7]; return (u16)MMU.reg_IME[ARMCPU_ARM7];
@ -3969,6 +3981,9 @@ static u32 FASTCALL _MMU_ARM7_read32(u32 adr)
/* Address is an IO register */ /* Address is an IO register */
switch(adr) switch(adr)
{ {
case REG_RTC:
return (u32)rtcRead();
case REG_IME : case REG_IME :
return MMU.reg_IME[ARMCPU_ARM7]; return MMU.reg_IME[ARMCPU_ARM7];
case REG_IE : case REG_IE :

33
desmume/src/rtc.cpp
View File

@ -70,8 +70,9 @@ static void rtcRecv()
{ {
case 0: // status register 1 case 0: // status register 1
//INFO("RTC: read regstatus1 (0x%02X)\n", rtc.regStatus1); //INFO("RTC: read regstatus1 (0x%02X)\n", rtc.regStatus1);
rtc.regStatus1 &= 0x0F;
rtc.data[0] = rtc.regStatus1; rtc.data[0] = rtc.regStatus1;
rtc.regStatus1 &= 0x7F; //rtc.regStatus1 &= 0x7F;
break; break;
case 1: // status register 2 case 1: // status register 2
//INFO("RTC: read regstatus2 (0x%02X)\n", rtc.regStatus1); //INFO("RTC: read regstatus2 (0x%02X)\n", rtc.regStatus1);
@ -135,18 +136,19 @@ static void rtcSend()
{ {
case 0: // status register 1 case 0: // status register 1
//INFO("RTC: write regstatus1 0x%02X\n", rtc.data[0]); //INFO("RTC: write regstatus1 0x%02X\n", rtc.data[0]);
rtc.regStatus1 &= 0xF1; // rtc.regStatus1 &= 0xF1;
rtc.regStatus1 |= (rtc.data[0] | 0x0E); // rtc.regStatus1 |= (rtc.data[0] | 0x0E);
rtc.regStatus1 = rtc.data[0];
break; break;
case 1: // status register 2 case 1: // status register 2
//INFO("RTC: write regstatus2 0x%02X\n", rtc.data[0]); //INFO("RTC: write regstatus2 0x%02X\n", rtc.data[0]);
rtc.regStatus2 = rtc.data[0]; rtc.regStatus2 = rtc.data[0];
break; break;
case 2: // date & time case 2: // date & time
//INFO("RTC: write date & time\n"); //INFO("RTC: write date & time : %02X %02X %02X %02X %02X %02X %02X\n", rtc.data[0], rtc.data[1], rtc.data[2], rtc.data[3], rtc.data[4], rtc.data[5], rtc.data[6]);
break; break;
case 3: // time case 3: // time
//INFO("RTC: write time\n"); //INFO("RTC: write time : %02X %02X %02X\n", rtc.data[0], rtc.data[1], rtc.data[2]);
break; break;
case 4: // freq/alarm 1 case 4: // freq/alarm 1
/*if (cmdBitsSize[0x04] == 8) /*if (cmdBitsSize[0x04] == 8)
@ -174,7 +176,7 @@ void rtcInit()
rtc.regStatus1 |= 0x02; rtc.regStatus1 |= 0x02;
} }
u8 rtcRead() u16 rtcRead()
{ {
//INFO("MMU Read RTC 0x%02X (%03i)\n", rtc._REG, rtc.bitsCount); //INFO("MMU Read RTC 0x%02X (%03i)\n", rtc._REG, rtc.bitsCount);
return (rtc._REG); return (rtc._REG);
@ -213,15 +215,20 @@ void rtcWrite(u16 val)
rtc.bitsCount ++; rtc.bitsCount ++;
if (rtc.bitsCount == 7) if (rtc.bitsCount == 7)
{ {
if ( (rtc.cmd & 0x06) != 0x06 ) // Little-endian command
if((rtc.cmd & 0x0F) == 0x06)
{ {
rtc.cmdStat = 0; rtc.cmdStat = 2;
//INFO("RTC uknown command 0x02%X\n", rtc.cmd); u8 tmp = rtc.cmd;
break; rtc.cmd = ((tmp & 0x40) >> 6) | ((tmp & 0x20) >> 4) | ((tmp & 0x10) >> 2);
}
// Big-endian command
else
{
rtc.cmdStat = 2;
rtc.cmd >>= 1;
rtc.cmd &= 0x07;
} }
rtc.cmdStat = 2;
rtc.cmd >>= 4;
rtc.cmd &= 0x07;
//INFO("RTC command 0x%02X\n", rtc.cmd); //INFO("RTC command 0x%02X\n", rtc.cmd);
} }

2
desmume/src/rtc.h
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@ -28,6 +28,6 @@
#include "types.h" #include "types.h"
extern void rtcInit(); extern void rtcInit();
extern u8 rtcRead(); extern u16 rtcRead();
extern void rtcWrite(u16 val); extern void rtcWrite(u16 val);
#endif #endif