completely rewrite ARDS processing. definitely fix some bugs. probably create some more. overall clarity level increased
This commit is contained in:
zeromus
parent
9d6e52acac
commit
6abf2b3454
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@ -71,338 +71,452 @@ BOOL CHEATS::update(u8 size, u32 address, u32 val, char *description, BOOL enabl
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return TRUE;
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}
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#define CHEATLOG(...)
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//#define CHEATLOG(...) printf(__VA_ARGS__)
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void CHEATS::ARparser(CHEATS_LIST& list)
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{
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u8 type = 0;
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u8 subtype = 0;
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u32 hi = 0;
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u32 lo = 0;
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u32 addr = 0;
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u32 val = 0;
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// AR temporary vars & flags
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u32 offset = 0;
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u32 datareg = 0;
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u32 loopcount = 0;
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u32 counter = 0;
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u32 if_flag = 0;
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s32 loopbackline = 0;
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u32 loop_flag = 0;
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//primary organizational source (seems to be referenced by cheaters the most) - http://doc.kodewerx.org/hacking_nds.html
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//secondary clarification and details (for programmers) - http://problemkaputt.de/gbatek.htm#dscartcheatactionreplayds
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//general note: gbatek is more precise with the maths; it does not indicate any special wraparound/masking behaviour so it's assumed to be standard 32bit masking
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//general note: <gbatek> For all word/halfword accesses, the address should be aligned accordingly -- OR ELSE WHAT? (probably the default behaviour of our MMU interface)
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//TODO: "Code Hacks" from kodewerx (seems frail, but we should at least detect them and print some diagnostics
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//TODO: v154 special stuff
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bool v154 = false; //not supported yet
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for (int i=0; i < list.num; i++)
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struct {
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//LSB is
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u32 status;
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struct {
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//backup copy of status managed by loop commands
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u32 status;
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//loop counter index
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u32 idx;
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//loop iterations goal (runs rpt+1 times generally)
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u32 iterations;
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//target of loop
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u32 top;
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} loop;
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//registers
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u32 offset, data;
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} st;
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memset(&st,0,sizeof(st));
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CHEATLOG("-----------------------------------\n");
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for (u32 i=0; i < list.num; i++)
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{
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type = list.code[i][0] >> 28;
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subtype = (list.code[i][0] >> 24) & 0x0F;
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const u32 hi = list.code[i][0];
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const u32 lo = list.code[i][1];
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hi = list.code[i][0] & 0x0FFFFFFF;
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lo = list.code[i][1];
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CHEATLOG("executing [%02d] %08X %08X (ofs=%08X)\n",i, hi,lo, st.offset);
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if (if_flag > 0)
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//parse codes into types by kodewerx standards
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u32 type = list.code[i][0] >> 28;
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//these two are broken down into subtypes
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if(type == 0x0C || type == 0x0D)
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type = list.code[i][0] >> 24;
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//process current execution status:
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u32 statusSkip = st.status & 1;
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//<gbatek> The condition register is checked, for all code types but the D0, D1 and D2 code type
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//<gbatek> and for the C5 code type it's checked AFTER the counter has been incremented (so the counter is always incremented)
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//but first: we must run this for IFs regardless of the condition flag to track the nest level
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if(type >= 0x03 && type <= 0x0A)
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{
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if (type == 0x0E) i += ((lo + 7) / 8);
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if ( (type == 0x0D) && (subtype == 0)) if_flag--; // ENDIF
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if ( (type == 0x0D) && (subtype == 2)) // NEXT & Flush
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{
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if (loop_flag)
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i = (loopbackline-1);
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else
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{
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offset = 0;
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datareg = 0;
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loopcount = 0;
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counter = 0;
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if_flag = 0;
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loop_flag = 0;
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}
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//pretty wild guess as to how this is implemented (I could be off by one)
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//we begin by assuming the current status is disabled, since we wont have a chance to correct if this IF is not supposed to be evaluated
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st.status = (st.status<<1) | 1;
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}
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if(type == 0xD0 || type == 0xD1 || type == 0xD2) {}
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else if(type == 0xC5) {}
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else
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{
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if(statusSkip) {
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CHEATLOG(" (skip!)\n");
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continue;
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}
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continue;
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}
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switch (type)
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u32 operand,x,y,z,addr;
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switch(type)
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{
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case 0x00:
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case 0x00:
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//(hi == 0x00000000) implies: "manual hook code" -- sometimes
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//maybe a type "M" code -- impossible to enter into desmume? not supported right now.
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//otherwise:
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//32-bit (Constant RAM Writes)
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//0XXXXXXX YYYYYYYY
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//Writes word YYYYYYYY to [XXXXXXX+offset].
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x = hi & 0x0FFFFFFF;
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y = lo;
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addr = x + st.offset;
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_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, y);
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break;
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case 0x01:
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//16-bit (Constant RAM Writes)
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//1XXXXXXX 0000YYYY
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//Writes halfword YYYY to [XXXXXXX+offset].
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x = hi & 0x0FFFFFFF;
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y = lo & 0xFFFF;
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addr = x + st.offset;
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_MMU_write16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, y);
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break;
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case 0x02:
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//8-bit (Constant RAM Writes)
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//2XXXXXXX 000000YY
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//Writes byte YY to [XXXXXXX+offset].
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x = hi & 0x0FFFFFFF;
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y = lo & 0xFF;
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addr = x + st.offset;
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_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, y);
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break;
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case 0x03:
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//Greater Than (Conditional 32-Bit Code Types)
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//3XXXXXXX YYYYYYYY
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//Checks if YYYYYYYY > (word at [XXXXXXX])
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y > operand) st.status &= ~1;
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break;
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case 0x04:
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//Less Than (Conditional 32-Bit Code Types)
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//4XXXXXXX YYYYYYYY
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//Checks if YYYYYYYY < (word at [XXXXXXX])
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y < operand) st.status &= ~1;
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break;
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case 0x05:
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//Equal To (Conditional 32-Bit Code Types)
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//5XXXXXXX YYYYYYYY
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//Checks if YYYYYYYY == (word at [XXXXXXX])
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y == operand) st.status &= ~1;
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break;
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case 0x06:
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//Not Equal To (Conditional 32-Bit Code Types)
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//6XXXXXXX YYYYYYYY
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//Checks if YYYYYYYY != (word at [XXXXXXX])
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y != operand) st.status &= ~1;
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break;
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case 0x07:
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//Greater Than (Conditional 16-Bit + Masking RAM Writes)
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//7XXXXXXX ZZZZYYYY
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//Checks if (YYYY) > (not (ZZZZ) & halfword at [XXXX]).
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo&0xFFFF;
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z = lo>>16;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y > ( (~z) & operand) ) st.status &= ~1;
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break;
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case 0x08:
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//Less Than (Conditional 16-Bit + Masking RAM Writes)
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//8XXXXXXX ZZZZYYYY
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//Checks if (YYYY) < (not (ZZZZ) & halfword at [XXXX]).
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo&0xFFFF;
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z = lo>>16;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y < ( (~z) & operand) ) st.status &= ~1;
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break;
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case 0x09:
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//Equal To (Conditional 16-Bit + Masking RAM Writes)
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//9XXXXXXX ZZZZYYYY
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//Checks if (YYYY) == (not (ZZZZ) & halfword at [XXXX]).
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo&0xFFFF;
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z = lo>>16;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y == ( (~z) & operand) ) st.status &= ~1;
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break;
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case 0x0A:
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//Not Equal To (Conditional 16-Bit + Masking RAM Writes)
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//AXXXXXXX ZZZZYYYY
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//Checks if (YYYY) != (not (ZZZZ) & halfword at [XXXX]).
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//If not, the code(s) following this one are not executed (ie. execution status is set to false) until a code type D0 or D2 is encountered, or until the end of the code list is reached.
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x = hi & 0x0FFFFFFF;
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y = lo&0xFFFF;
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z = lo>>16;
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if(v154) if(x == 0) x = st.offset;
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operand = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(x);
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if(y != ( (~z) & operand) ) st.status &= ~1;
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break;
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case 0x0B:
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//Load offset (Offset Codes)
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//BXXXXXXX 00000000
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//Loads the 32-bit value into the 'offset'.
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//Offset = word at [0XXXXXXX + offset].
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x = hi & 0x0FFFFFFF;
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addr = x + st.offset;
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st.offset = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
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break;
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case 0xC0:
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//(Loop Code)
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//C0000000 YYYYYYYY
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//This sets the 'Dx repeat value' to YYYYYYYY and saves the 'Dx nextcode to be executed' and the 'Dx execution status'. Repeat will be executed when a D1/D2 code is encountered.
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//When repeat is executed, the AR reloads the 'next code to be executed' and the 'execution status' from the Dx registers.
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//<gbatek> FOR loopcount=0 to YYYYYYYY ;execute Y+1 times
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y = lo;
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st.loop.idx = 0; //<gbatek> any FOR statement does forcefully terminate any prior loop
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st.loop.iterations = y;
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st.loop.top = i; //current instruction is saved as top for branching back up
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//<gbatek> FOR does backup the current IF condidition flags, and NEXT does restore these flags
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st.loop.status = st.status;
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break;
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case 0xD0:
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//Terminator (Special Codes)
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//D0000000 00000000
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//Loads the previous execution status. If none exists, the execution status stays at 'execute codes'
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//wild guess as to fine details of how this is implemented
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st.status >>= 1;
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//"If none exists, the execution status stays at 'execute codes'."
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//0 will be shifted in, so execution will always proceed
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//in other words, a stack underflow results in the original state of execution
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break;
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case 0xD1:
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//Loop execute variant (Special Codes)
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//D1000000 00000000
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//Executes the next block of codes 'n' times (specified by the 0x0C codetype), but doesn't clear the Dx register upon completion.
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//<gbatek> FOR does backup the current IF condidition flags, and NEXT does restore these flags
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st.status = st.loop.status;
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if(st.loop.idx < st.loop.iterations)
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{
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if (hi==0)
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st.loop.idx++;
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i = st.loop.top;
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}
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break;
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case 0xD2:
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//Loop Execute Variant/ Full Terminator (Special Codes)
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//D2000000 00000000
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//Executes the next block of codes 'n' times (specified by the 0x0C codetype), and clears all temporary data. (i.e. execution status, offsets, code C settings, etc.)
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//This code can also be used as a full terminator, giving the same effects to any block of code.
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//<gbatek> FOR does backup the current IF condidition flags, and NEXT does restore these flags
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st.status = st.loop.status;
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if(st.loop.idx < st.loop.iterations)
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{
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st.loop.idx++;
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i = st.loop.top;
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}
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else
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{
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//<gbatek> The NEXT+FLUSH command does (after finishing the loop) reset offset=0, datareg=0, and does clear all condition flags, so further ENDIF(s) aren't required after the loop.
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memset(&st,0,sizeof(st));
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}
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break;
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case 0xD3:
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//Set offset (Offset Codes)
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//D3000000 XXXXXXXX
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//Sets the offset value to XXXXXXXX.
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x = lo;
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st.offset = x;
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break;
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case 0xD4:
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//Add Value (Data Register Codes)
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//D4000000 XXXXXXXX
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//Adds 'XXXXXXXX' to the data register used by codetypes 0xD6 - 0xDB.
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//<gbatek> datareg = datareg + XXXXXXXX
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x = lo;
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st.data += x;
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break;
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case 0xD5:
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//Set Value (Data Register Codes)
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//D5000000 XXXXXXXX
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//Set 'XXXXXXXX' to the data register used by code types 0xD6 - 0xD8.
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x = lo;
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st.data = x;
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break;
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case 0xD6:
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//32-Bit Incrementive Write (Data Register Codes)
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//D6000000 XXXXXXXX
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//Writes the 'Dx data' word to [XXXXXXXX+offset], and increments the offset by 4.
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//<gbatek> word[XXXXXXXX+offset]=datareg, offset=offset+4
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x = lo;
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addr = x + st.offset;
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_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, st.data);
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st.offset += 4;
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break;
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case 0xD7:
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//16-Bit Incrementive Write (Data Register Codes)
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//D7000000 XXXXXXXX
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//Writes the 'Dx data' halfword to [XXXXXXXX+offset], and increments the offset by 2.
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//<gbatek> half[XXXXXXXX+offset]=datareg, offset=offset+2
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x = lo;
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addr = x + st.offset;
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_MMU_write16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, st.data);
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st.offset += 2;
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break;
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case 0xD8:
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//8-Bit Incrementive Write (Data Register Codes)
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//D8000000 XXXXXXXX
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//Writes the 'Dx data' byte to [XXXXXXXX+offset], and increments the offset by 1.
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//<gbatek> byte[XXXXXXXX+offset]=datareg, offset=offset+1
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x = lo;
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addr = x + st.offset;
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_MMU_write16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, st.data);
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st.offset += 1;
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break;
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case 0xD9:
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//32-Bit Load (Data Register Codes)
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//D9000000 XXXXXXXX
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//Loads the word at [XXXXXXXX+offset] and stores it in the'Dx data register'.
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x = lo;
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addr = x + st.offset;
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st.data = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
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break;
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case 0xDA:
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//16-Bit Load (Data Register Codes)
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//DA000000 XXXXXXXX
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//Loads the halfword at [XXXXXXXX+offset] and stores it in the'Dx data register'.
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x = lo;
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addr = x + st.offset;
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st.data = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
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break;
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case 0xDB:
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//8-Bit Load (Data Register Codes)
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//DB000000 XXXXXXXX
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//Loads the byte at [XXXXXXXX+offset] and stores it in the'Dx data register'.
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//This is a bugged code type. Check 'AR Hack #0' for the fix.
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x = lo;
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addr = x + st.offset;
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st.data = _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
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//<gbatek> Before v1.54, the DB000000 code did accidently set offset=offset+XXXXXXX after execution of the code
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if(!v154)
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st.offset = addr;
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break;
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case 0xDC:
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//Set offset (Offset Codes)
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//DC000000 XXXXXXXX
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//Adds an offset to the current offset. (Dual Offset)
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x = lo;
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||||
st.offset += x;
|
||||
break;
|
||||
|
||||
case 0x0E:
|
||||
//Patch Code (Miscellaneous Memory Manipulation Codes)
|
||||
//EXXXXXXX YYYYYYYY
|
||||
//Copies YYYYYYYY bytes from (current code location + 8) to [XXXXXXXX + offset].
|
||||
//<gbatek> Copy YYYYYYYY parameter bytes to [XXXXXXXX+offset...]
|
||||
//<gbatek> For the COPY commands, addresses should be aligned by four (all data is copied with ldr/str, except, on odd lengths, the last 1..3 bytes do use ldrb/strb).
|
||||
//attempting to emulate logic the way they may have implemented it, just in case
|
||||
x = hi & 0x0FFFFFFF;
|
||||
y = lo;
|
||||
addr = x + st.offset;
|
||||
|
||||
{
|
||||
u32 j=0,t=0,b=0;
|
||||
while(y>=4)
|
||||
{
|
||||
//manual hook
|
||||
u32 tmp = list.code[i][t];
|
||||
if(t==1) i++;
|
||||
t ^= 1;
|
||||
_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr,tmp);
|
||||
addr += 4;
|
||||
y -= 4;
|
||||
}
|
||||
else
|
||||
if ((hi==0x0000AA99) && (lo==0)) // 0000AA99 00000000 parameter bytes 9..10 for above code (padded with 00s)
|
||||
while(y>0)
|
||||
{
|
||||
//parameter bytes 9..10 for above code (padded with 00s)
|
||||
}
|
||||
else // 0XXXXXXX YYYYYYYY word[XXXXXXX+offset] = YYYYYYYY
|
||||
{
|
||||
addr = hi + offset;
|
||||
_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, lo);
|
||||
u32 tmp = list.code[i][t]>>b;
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr,tmp);
|
||||
addr += 1;
|
||||
y -= 1;
|
||||
b += 4;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: // 1XXXXXXX 0000YYYY half[XXXXXXX+offset] = YYYY
|
||||
addr = hi + offset;
|
||||
_MMU_write16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, lo);
|
||||
break;
|
||||
|
||||
case 0x02: // 2XXXXXXX 000000YY byte[XXXXXXX+offset] = YY
|
||||
addr = hi + offset;
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, lo);
|
||||
break;
|
||||
|
||||
case 0x03: // 3XXXXXXX YYYYYYYY IF YYYYYYYY > word[XXXXXXX] ;unsigned
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( lo > val )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x04: // 4XXXXXXX YYYYYYYY IF YYYYYYYY < word[XXXXXXX] ;unsigned
|
||||
if ((hi == 0x04332211) && (lo == 88776655)) //44332211 88776655 parameter bytes 1..8 for above code (example)
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( lo < val )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x05: // 5XXXXXXX YYYYYYYY IF YYYYYYYY = word[XXXXXXX]
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( lo == val )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x06: // 6XXXXXXX YYYYYYYY IF YYYYYYYY <> word[XXXXXXX]
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( lo != val )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x07: // 7XXXXXXX ZZZZYYYY IF YYYY > ((not ZZZZ) AND half[XXXXXXX])
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( (lo & 0xFFFF) > ( (~(lo >> 16)) & val) )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x08: // 8XXXXXXX ZZZZYYYY IF YYYY < ((not ZZZZ) AND half[XXXXXXX])
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( (lo & 0xFFFF) < ( (~(lo >> 16)) & val) )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x09: // 9XXXXXXX ZZZZYYYY IF YYYY = ((not ZZZZ) AND half[XXXXXXX])
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( (lo & 0xFFFF) == ( (~(lo >> 16)) & val) )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x0A: // AXXXXXXX ZZZZYYYY IF YYYY <> ((not ZZZZ) AND half[XXXXXXX])
|
||||
if (hi == 0) hi = offset; // V1.54+
|
||||
val = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(hi);
|
||||
if ( (lo & 0xFFFF) != ( (~(lo >> 16)) & val) )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x0B: // BXXXXXXX 00000000 offset = word[XXXXXXX+offset]
|
||||
addr = hi + offset;
|
||||
offset = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);;
|
||||
break;
|
||||
|
||||
case 0x0C:
|
||||
switch (subtype)
|
||||
{
|
||||
case 0x0: // C0000000 YYYYYYYY FOR loopcount=0 to YYYYYYYY ;execute Y+1 times
|
||||
if (loopcount < (lo+1))
|
||||
loop_flag = 1;
|
||||
else
|
||||
loop_flag = 0;
|
||||
loopcount++;
|
||||
loopbackline = i;
|
||||
break;
|
||||
|
||||
case 0x4: // C4000000 00000000 offset = address of the C4000000 code ; V1.54
|
||||
printf("AR: untested code C4\n");
|
||||
break;
|
||||
|
||||
case 0x5: // C5000000 XXXXYYYY counter=counter+1, IF (counter AND YYYY) = XXXX ; V1.54
|
||||
counter++;
|
||||
if ( (counter & (lo & 0xFFFF)) == ((lo >> 8) & 0xFFFF) )
|
||||
{
|
||||
if (if_flag > 0) if_flag--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if_flag++;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x6: // C6000000 XXXXXXXX [XXXXXXXX]=offset ; V1.54
|
||||
_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(lo, offset);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x0D:
|
||||
case 0x0F:
|
||||
//Memory Copy Code (Miscellaneous Memory Manipulation Codes)
|
||||
//FXXXXXXX YYYYYYYY
|
||||
//<gbatek> Copy YYYYYYYY bytes from [offset..] to [XXXXXXX...]
|
||||
//<gbatek> For the COPY commands, addresses should be aligned by four (all data is copied with ldr/str, except, on odd lengths, the last 1..3 bytes do use ldrb/strb).
|
||||
//attempting to emulate logic the way they may have implemented it, just in case
|
||||
x = hi & 0x0FFFFFFF;
|
||||
y = lo;
|
||||
addr = x;
|
||||
while(y>=4)
|
||||
{
|
||||
switch (subtype)
|
||||
{
|
||||
case 0x0: // D0000000 00000000 ENDIF
|
||||
break;
|
||||
|
||||
case 0x1: // D1000000 00000000 NEXT loopcount
|
||||
if (loop_flag)
|
||||
i = (loopbackline-1);
|
||||
break;
|
||||
|
||||
case 0x2: // D2000000 00000000 NEXT loopcount, and then FLUSH everything
|
||||
if (loop_flag)
|
||||
i = (loopbackline-1);
|
||||
else
|
||||
{
|
||||
offset = 0;
|
||||
datareg = 0;
|
||||
loopcount = 0;
|
||||
counter = 0;
|
||||
if_flag = 0;
|
||||
loop_flag = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x3: // D3000000 XXXXXXXX offset = XXXXXXXX
|
||||
offset = lo;
|
||||
break;
|
||||
|
||||
case 0x4: // D4000000 XXXXXXXX datareg = datareg + XXXXXXXX
|
||||
datareg += lo;
|
||||
break;
|
||||
|
||||
case 0x5: // D5000000 XXXXXXXX datareg = XXXXXXXX
|
||||
datareg = lo;
|
||||
break;
|
||||
|
||||
case 0x6: // D6000000 XXXXXXXX word[XXXXXXXX+offset]=datareg, offset=offset+4
|
||||
addr = lo + offset;
|
||||
_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, datareg);
|
||||
offset += 4;
|
||||
break;
|
||||
|
||||
case 0x7: // D7000000 XXXXXXXX half[XXXXXXXX+offset]=datareg, offset=offset+2
|
||||
addr = lo + offset;
|
||||
_MMU_write16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, datareg);
|
||||
offset += 2;
|
||||
break;
|
||||
|
||||
case 0x8: // D8000000 XXXXXXXX byte[XXXXXXXX+offset]=datareg, offset=offset+1
|
||||
addr = lo + offset;
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, datareg);
|
||||
offset += 1;
|
||||
break;
|
||||
|
||||
case 0x9: // D9000000 XXXXXXXX datareg = word[XXXXXXXX+offset]
|
||||
addr = lo + offset;
|
||||
datareg = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
|
||||
break;
|
||||
|
||||
case 0xA: // DA000000 XXXXXXXX datareg = half[XXXXXXXX+offset]
|
||||
addr = lo + offset;
|
||||
datareg = _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
|
||||
break;
|
||||
|
||||
case 0xB: // DB000000 XXXXXXXX datareg = byte[XXXXXXXX+offset] ;bugged on pre-v1.54
|
||||
addr = lo + offset;
|
||||
datareg = _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
|
||||
break;
|
||||
|
||||
case 0xC: // DC000000 XXXXXXXX offset = offset + XXXXXXXX
|
||||
offset += lo;
|
||||
break;
|
||||
}
|
||||
u32 tmp = _MMU_read32<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
|
||||
_MMU_write32<ARMCPU_ARM7,MMU_AT_DEBUG>(y,tmp);
|
||||
addr += 4;
|
||||
y -= 4;
|
||||
}
|
||||
while(y>0)
|
||||
{
|
||||
u8 tmp = _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr);
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(y,tmp);
|
||||
addr += 1;
|
||||
y -= 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xE: // EXXXXXXX YYYYYYYY Copy YYYYYYYY parameter bytes to [XXXXXXXX+offset...]
|
||||
{
|
||||
u8 *tmp_code = (u8*)(list.code[i+1]);
|
||||
u32 addr = hi+offset;
|
||||
u32 maxByteReadLocation = ((2 * 4) * (MAX_XX_CODE - i - 1)) - 1; // 2 = 2 array dimensions, 4 = 4 bytes per array element
|
||||
|
||||
if (lo <= maxByteReadLocation)
|
||||
{
|
||||
for (u32 t = 0; t < lo; t++)
|
||||
{
|
||||
u8 tmp = tmp_code[t];
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr, tmp);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
i += ((lo + 7) / 8);
|
||||
}
|
||||
default:
|
||||
printf("AR: ERROR unknown command %08X %08X\n", hi, lo);
|
||||
break;
|
||||
|
||||
case 0xF: // FXXXXXXX YYYYYYYY Copy YYYYYYYY bytes from [offset..] to [XXXXXXX...]
|
||||
for (u32 t = 0; t < lo; t++)
|
||||
{
|
||||
u8 tmp = _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(offset+t);
|
||||
_MMU_write08<ARMCPU_ARM7,MMU_AT_DEBUG>(hi+t, tmp);
|
||||
}
|
||||
break;
|
||||
default: PROGINFO("AR: ERROR unknown command 0x%2X at %08X:%08X\n", type, hi, lo); break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
BOOL CHEATS::add_AR_Direct(CHEATS_LIST cheat)
|
||||
|
|
|
|||
Loading…
Reference in New Issue