- add mmu to savestate.
- totally change how the savestates work in order to fix a bug in the gfx3d savestate. your old savestates are definitely invalidated. - rename adress to address everywhere.
This commit is contained in:
zeromus
parent
a45b610c70
commit
6a696d6bb8
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@ -2011,6 +2011,7 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
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/* initialize the scanline black */
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/* not doing this causes invalid colors when all active BGs are prevented to draw at some place */
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//ZERO TODO - shouldnt this be BG palette color 0?
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memset(dst,0,256*2) ;
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// This could almost be changed to use function pointers
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@ -647,7 +647,7 @@ u16 FASTCALL _MMU_read16(u32 adr)
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if(adr&0x04000000)
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{
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/* Adress is an IO register */
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/* Address is an IO register */
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switch(adr)
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{
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case 0x04000604:
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@ -721,7 +721,7 @@ u32 FASTCALL _MMU_read32(u32 adr)
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if((adr >> 24) == 4)
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{
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/* Adress is an IO register */
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/* Address is an IO register */
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switch(adr)
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{
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// This is hacked due to the only current 3D core
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@ -826,10 +826,10 @@ u32 FASTCALL _MMU_read32(u32 adr)
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{
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u32 val=0;
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if(MMU.dscard[proc].adress)
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val = T1ReadLong(MMU.CART_ROM, MMU.dscard[proc].adress);
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if(MMU.dscard[proc].address)
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val = T1ReadLong(MMU.CART_ROM, MMU.dscard[proc].address);
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MMU.dscard[proc].adress += 4; /* increment adress */
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MMU.dscard[proc].address += 4; /* increment address */
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MMU.dscard[proc].transfer_count--; /* update transfer counter */
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if(MMU.dscard[proc].transfer_count) /* if transfer is not ended */
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@ -1306,7 +1306,7 @@ void FASTCALL _MMU_write16(u32 adr, u16 val)
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((u16 *)(MMU.MMU_MEM[proc][0x40]))[(adr-0x04000000)>>1] = val;
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gfx3d_UpdateToonTable(&((MMU.MMU_MEM[proc][0x40]))[(0x380)]);
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}
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/* Adress is an IO register */
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/* Address is an IO register */
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else switch(adr)
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{
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case 0x0400035C:
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@ -2843,7 +2843,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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if(MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB7)
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{
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MMU.dscard[proc].adress = (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+4));
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MMU.dscard[proc].address = (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+4));
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MMU.dscard[proc].transfer_count = 0x80;// * ((val>>24)&7));
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}
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else if (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB8)
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@ -2851,7 +2851,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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// Get ROM chip ID
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val |= 0x800000; // Data-Word Status
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T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val);
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MMU.dscard[proc].adress = 0;
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MMU.dscard[proc].address = 0;
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}
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else
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{
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@ -2861,7 +2861,7 @@ void FASTCALL _MMU_write32(u32 adr, u32 val)
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//CARDLOG("%08X : %08X %08X\r\n", adr, val, adresse[proc]);
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val |= 0x00800000;
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if(MMU.dscard[proc].adress == 0)
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if(MMU.dscard[proc].address == 0)
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{
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val &= ~0x80000000;
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T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val);
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@ -33,7 +33,7 @@
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extern char szRomPath[512];
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extern char szRomBaseName[512];
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/* theses macros are designed for reading/writing in memory (m is a pointer to memory, like MMU.MMU_MEM[proc], and a is an adress, like 0x04000000 */
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/* theses macros are designed for reading/writing in memory (m is a pointer to memory, like MMU.MMU_MEM[proc], and a is an address, like 0x04000000 */
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#define MEM_8(m, a) (((u8*)(m[((a)>>20)&0xff]))[((a)&0xfff)])
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/* theses ones for reading in rom data */
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@ -43,60 +43,59 @@ extern char szRomBaseName[512];
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//#define MAIN_MEMORY_DISP_FIFO 2
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typedef struct {
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//ARM7 mem
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u8 ARM7_BIOS[0x4000];
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u8 ARM7_ERAM[0x10000];
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u8 ARM7_REG[0x10000];
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u8 ARM7_WIRAM[0x10000];
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//ARM7 mem
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u8 ARM7_BIOS[0x4000];
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u8 ARM7_ERAM[0x10000];
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u8 ARM7_REG[0x10000];
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u8 ARM7_WIRAM[0x10000];
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u8 vram_mode[9];
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u8 vScreen;
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//Shared ram
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u8 SWIRAM[0x8000];
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//Card rom & ram
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u8 * CART_ROM;
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u8 CART_RAM[0x10000];
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//Shared ram
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u8 SWIRAM[0x8000];
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//Card rom & ram
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u8 * CART_ROM;
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u8 CART_RAM[0x10000];
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//Unused ram
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u8 UNUSED_RAM[4];
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u8 * * MMU_MEM[2];
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u32 * MMU_MASK[2];
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u8 ARM9_RW_MODE;
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u8 * * MMU_MEM[2];
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u32 * MMU_MASK[2];
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u8 ARM9_RW_MODE;
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FIFO fifos[2]; // 0 - ARM9 FIFO
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// 1 - ARM7 FIFO
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FIFO fifos[2]; // 0 - ARM9 FIFO
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// 1 - ARM7 FIFO
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u32 * MMU_WAIT16[2];
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u32 * MMU_WAIT32[2];
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u32 * MMU_WAIT16[2];
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u32 * MMU_WAIT32[2];
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u32 DTCMRegion;
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u32 ITCMRegion;
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u16 timer[2][4];
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s32 timerMODE[2][4];
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u32 timerON[2][4];
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u32 timerRUN[2][4];
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u16 timerReload[2][4];
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u32 reg_IME[2];
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u32 reg_IE[2];
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u32 reg_IF[2];
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u32 DMAStartTime[2][4];
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s32 DMACycle[2][4];
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u32 DMACrt[2][4];
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BOOL DMAing[2][4];
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memory_chip_t fw;
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memory_chip_t bupmem;
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nds_dscard dscard[2];
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u32 CheckTimers;
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u32 CheckDMAs;
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u32 DTCMRegion;
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u32 ITCMRegion;
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u16 timer[2][4];
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s32 timerMODE[2][4];
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u32 timerON[2][4];
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u32 timerRUN[2][4];
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u16 timerReload[2][4];
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u32 reg_IME[2];
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u32 reg_IE[2];
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u32 reg_IF[2];
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u32 DMAStartTime[2][4];
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s32 DMACycle[2][4];
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u32 DMACrt[2][4];
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BOOL DMAing[2][4];
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memory_chip_t fw;
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memory_chip_t bupmem;
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nds_dscard dscard[2];
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u32 CheckTimers;
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u32 CheckDMAs;
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} MMU_struct;
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@ -1502,7 +1502,7 @@ bool spu_loadstate(std::istream* is)
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//copy the core spu (the more accurate) to the user spu
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if(SPU_user) {
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memcpy(SPU_core->channels,SPU_user->channels,sizeof(SPU_core->channels));
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memcpy(SPU_user->channels,SPU_core->channels,sizeof(SPU_core->channels));
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}
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return true;
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@ -23,7 +23,7 @@
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typedef struct
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{
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u32 adress;
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u32 address;
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u32 transfer_count;
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} nds_dscard;
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@ -1472,71 +1472,71 @@ void gfx3d_glGetLightColor(unsigned int index, unsigned int* dest)
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SFORMAT SF_GFX3D[]={
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{ &control, 4|SS_RLSB, "GCTL" },
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{ &polyAttr, 4|SS_RLSB, "GPAT" },
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{ &textureFormat, 4|SS_RLSB, "GTFM" },
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{ &texturePalette, 4|SS_RLSB, "GTPA" },
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{ &mode, 4|SS_RLSB, "GMOD" },
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{ mtxTemporal, 4|SS_MULT(16), "GMTM" },
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{ mtxCurrent, 4|SS_MULT(64), "GMCU" },
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{ &mtxStack[0].position, 4|SS_RLSB, "GM0P" },
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{ mtxStack[0].matrix, 4|SS_MULT(16), "GM1M" },
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{ &mtxStack[1].position, 4|SS_RLSB, "GM1P" },
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{ mtxStack[1].matrix, 4|SS_MULT(16*31), "GM1M" },
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{ &mtxStack[2].position, 4|SS_RLSB, "GM2P" },
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{ mtxStack[2].matrix, 4|SS_MULT(16*31), "GM2M" },
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{ &mtxStack[3].position, 4|SS_RLSB, "GM3P" },
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{ mtxStack[3].matrix, 4|SS_MULT(16), "GM3M" },
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{ &ML4x4ind, 1, "ML4I" },
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{ &ML4x3_c, 1, "ML3C" },
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{ &ML4x3_l, 1, "ML3L" },
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{ &MM4x4ind, 1, "MM4I" },
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{ &MM4x3_c, 1, "MM3C" },
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{ &MM4x3_l, 1, "MM3L" },
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{ &MM3x3_c, 1, "MMxC" },
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{ &MM3x3_l, 1, "MMxL" },
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{ coord, 4|SS_MULT(4), "GCOR" },
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{ &coordind, 1, "GCOI" },
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{ &vtxFormat, 4|SS_RLSB, "GCOI" },
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{ trans, 4|SS_MULT(4), "GTRN" },
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{ &transind, 1, "GTRI" },
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{ scale, 4|SS_MULT(4), "GSCA" },
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{ &scaleind, 1, "GSCI" },
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{ &_t, 4|SS_RLSB, "G_T_" },
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{ &_s, 4|SS_RLSB, "G_S_" },
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{ &last_t, 4|SS_RLSB, "GL_T" },
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{ &last_s, 4|SS_RLSB, "GL_S" },
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{ &clCmd, 4|SS_RLSB, "GLCM" },
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{ &clInd, 4|SS_RLSB, "GLIN" },
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{ &clInd2, 4|SS_RLSB, "GLI2" },
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{ colorRGB, 4, "GCOL" },
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{ lightColor, 4|SS_MULT(4), "GLCO" },
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{ lightDirection, 4|SS_MULT(4), "GLDI" },
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{ &dsDiffuse, 2|SS_RLSB, "GMDI" },
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{ &dsAmbient, 2|SS_RLSB, "GMAM" },
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{ &dsSpecular, 2|SS_RLSB, "GMSP" },
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{ &dsEmission, 2|SS_RLSB, "GMEM" },
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{ &triStripToggle, 4|SS_RLSB, "GTST" },
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{ &listTwiddle, 4|SS_RLSB, "GLTW" },
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{ &flushPending, 4|SS_RLSB, "GFLP" },
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{ &gfx3d.enableTexturing, 4|SS_RLSB, "GSET" },
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{ &gfx3d.enableAlphaTest, 4|SS_RLSB, "GSEA" },
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{ &gfx3d.enableAlphaBlending, 4|SS_RLSB, "GSEB" },
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{ &gfx3d.enableAntialiasing, 4|SS_RLSB, "GSEX" },
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{ &gfx3d.enableEdgeMarking, 4|SS_RLSB, "GSEE" },
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{ &gfx3d.shading, 4|SS_RLSB, "GSSH" },
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{ &gfx3d.wbuffer, 4|SS_RLSB, "GSWB" },
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{ &gfx3d.sortmode, 4|SS_RLSB, "GSSM" },
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{ &gfx3d.alphaTestRef, 4|SS_RLSB, "GSAR" },
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{ &gfx3d.viewport.x, 4|SS_RLSB, "GSVX" },
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{ &gfx3d.viewport.y, 4|SS_RLSB, "GSVY" },
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{ &gfx3d.viewport.width, 4|SS_RLSB, "GSVW" },
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{ &gfx3d.viewport.height, 4|SS_RLSB, "GSVH" },
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{ gfx3d.clearColor, 4|SS_MULT(4), "GSCC" },
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{ &gfx3d.clearDepth , 4|SS_RLSB, "GSCD" },
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{ gfx3d.fogColor, 4|SS_MULT(4), "GSFC" },
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{ &gfx3d.fogOffset, 4|SS_RLSB, "GSFO" },
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{ gfx3d.rgbToonTable, 4|SS_MULT(32), "GSTT" },
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{ "GCTL", 4, 1, &control},
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{ "GPAT", 4, 1, &polyAttr},
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{ "GTFM", 4, 1, &textureFormat},
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{ "GTPA", 4, 1, &texturePalette},
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{ "GMOD", 4, 1, &mode},
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{ "GMTM", 4,16, mtxTemporal},
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{ "GMCU", 4,64, mtxCurrent},
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{ "GM0P", 4, 1, &mtxStack[0].position},
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{ "GM1M", 4,16, mtxStack[0].matrix},
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{ "GM1P", 4, 1, &mtxStack[1].position},
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{ "GM1M", 4,496,mtxStack[1].matrix},
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{ "GM2P", 4, 1, &mtxStack[2].position},
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{ "GM2M", 4,496,mtxStack[2].matrix},
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{ "GM3P", 4, 1, &mtxStack[3].position},
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{ "GM3M", 4,16, mtxStack[3].matrix},
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{ "ML4I", 1, 1, &ML4x4ind},
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{ "ML3C", 1, 1, &ML4x3_c},
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{ "ML3L", 1, 1, &ML4x3_l},
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{ "MM4I", 1, 1, &MM4x4ind},
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{ "MM3C", 1, 1, &MM4x3_c},
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{ "MM3L", 1, 1, &MM4x3_l},
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{ "MMxC", 1, 1, &MM3x3_c},
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{ "MMxL", 1, 1, &MM3x3_l},
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{ "GCOR", 4, 1, coord},
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{ "GCOI", 1, 1, &coordind},
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{ "GVFM", 4, 1, &vtxFormat},
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{ "GTRN", 4, 4, trans},
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{ "GTRI", 1, 1, &transind},
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{ "GSCA", 4, 4, scale},
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{ "GSCI", 1, 1, &scaleind},
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{ "G_T_", 4, 1, &_t},
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{ "G_S_", 4, 1, &_s},
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{ "GL_T", 4, 1, &last_t},
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{ "GL_S", 4, 1, &last_s},
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{ "GLCM", 4, 1, &clCmd},
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{ "GLIN", 4, 1, &clInd},
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{ "GLI2", 4, 1, &clInd2},
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{ "GCOL", 1, 4, colorRGB},
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{ "GLCO", 4, 4, lightColor},
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{ "GLDI", 4, 4, lightDirection},
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{ "GMDI", 2, 1, &dsDiffuse},
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{ "GMAM", 2, 1, &dsAmbient},
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{ "GMSP", 2, 1, &dsSpecular},
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{ "GMEM", 2, 1, &dsEmission},
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{ "GTST", 4, 1, &triStripToggle},
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{ "GLTW", 4, 1, &listTwiddle},
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{ "GFLP", 4, 1, &flushPending},
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{ "GSET", 4, 1, &gfx3d.enableTexturing},
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{ "GSEA", 4, 1, &gfx3d.enableAlphaTest},
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{ "GSEB", 4, 1, &gfx3d.enableAlphaBlending},
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{ "GSEX", 4, 1, &gfx3d.enableAntialiasing},
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{ "GSEE", 4, 1, &gfx3d.enableEdgeMarking},
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{ "GSSH", 4, 1, &gfx3d.shading},
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{ "GSWB", 4, 1, &gfx3d.wbuffer},
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{ "GSSM", 4, 1, &gfx3d.sortmode},
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{ "GSAR", 4, 1, &gfx3d.alphaTestRef},
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{ "GSVX", 4, 1, &gfx3d.viewport.x},
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{ "GSVY", 4, 1, &gfx3d.viewport.y},
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{ "GSVW", 4, 1, &gfx3d.viewport.width},
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{ "GSVH", 4, 1, &gfx3d.viewport.height},
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{ "GSCC", 4, 4, gfx3d.clearColor},
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{ "GSCD", 4, 1, &gfx3d.clearDepth},
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{ "GSFC", 4, 4, gfx3d.fogColor},
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{ "GSFO", 4, 1, &gfx3d.fogOffset},
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{ "GSTT", 4, 32, gfx3d.rgbToonTable},
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{ 0 }
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};
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@ -51,120 +51,188 @@ static const char* magic = "DeSmuME SState\0";
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SFORMAT SF_ARM7[]={
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{ &NDS_ARM7.instruction, 4|SS_RLSB, "7INS" },
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{ &NDS_ARM7.instruct_adr, 4|SS_RLSB, "7INA" },
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{ &NDS_ARM7.next_instruction, 4|SS_RLSB, "7INN" },
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{ NDS_ARM7.R, 4|SS_MULT(16), "7REG" },
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{ &NDS_ARM7.CPSR, 4|SS_RLSB, "7CPS" },
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{ &NDS_ARM7.SPSR, 4|SS_RLSB, "7SPS" },
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{ &NDS_ARM7.R13_usr, 4|SS_RLSB, "7DUS" },
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{ &NDS_ARM7.R14_usr, 4|SS_RLSB, "7EUS" },
|
||||
{ &NDS_ARM7.R13_svc, 4|SS_RLSB, "7DSV" },
|
||||
{ &NDS_ARM7.R14_svc, 4|SS_RLSB, "7ESV" },
|
||||
{ &NDS_ARM7.R13_abt, 4|SS_RLSB, "7DAB" },
|
||||
{ &NDS_ARM7.R14_abt, 4|SS_RLSB, "7EAB" },
|
||||
{ &NDS_ARM7.R13_und, 4|SS_RLSB, "7DUN" },
|
||||
{ &NDS_ARM7.R14_und, 4|SS_RLSB, "7EUN" },
|
||||
{ &NDS_ARM7.R13_irq, 4|SS_RLSB, "7DIR" },
|
||||
{ &NDS_ARM7.R14_irq, 4|SS_RLSB, "7EIR" },
|
||||
{ &NDS_ARM7.R8_fiq, 4|SS_RLSB, "78FI" },
|
||||
{ &NDS_ARM7.R9_fiq, 4|SS_RLSB, "79FI" },
|
||||
{ &NDS_ARM7.R10_fiq, 4|SS_RLSB, "7AFI" },
|
||||
{ &NDS_ARM7.R11_fiq, 4|SS_RLSB, "7BFI" },
|
||||
{ &NDS_ARM7.R12_fiq, 4|SS_RLSB, "7CFI" },
|
||||
{ &NDS_ARM7.R13_fiq, 4|SS_RLSB, "7DFI" },
|
||||
{ &NDS_ARM7.R14_fiq, 4|SS_RLSB, "7EFI" },
|
||||
{ &NDS_ARM7.SPSR_svc, 4|SS_RLSB, "7SVC" },
|
||||
{ &NDS_ARM7.SPSR_abt, 4|SS_RLSB, "7ABT" },
|
||||
{ &NDS_ARM7.SPSR_und, 4|SS_RLSB, "7UND" },
|
||||
{ &NDS_ARM7.SPSR_irq, 4|SS_RLSB, "7IRQ" },
|
||||
{ &NDS_ARM7.SPSR_fiq, 4|SS_RLSB, "7FIQ" },
|
||||
{ &NDS_ARM7.intVector, 4|SS_RLSB, "7int" },
|
||||
{ &NDS_ARM7.LDTBit, 1, "7LDT" },
|
||||
{ &NDS_ARM7.waitIRQ, 4|SS_RLSB, "7Wai" },
|
||||
{ &NDS_ARM7.wIRQ, 4|SS_RLSB, "7wIR" },
|
||||
{ &NDS_ARM7.wirq, 4|SS_RLSB, "7wir" },
|
||||
{ "7INS", 4, 1, &NDS_ARM7.instruction },
|
||||
{ "7INA", 4, 1, &NDS_ARM7.instruct_adr },
|
||||
{ "7INN", 4, 1, &NDS_ARM7.next_instruction },
|
||||
{ "7REG", 4,16, NDS_ARM7.R },
|
||||
{ "7CPS", 4, 1, &NDS_ARM7.CPSR },
|
||||
{ "7SPS", 4, 1, &NDS_ARM7.SPSR },
|
||||
{ "7DUS", 4, 1, &NDS_ARM7.R13_usr },
|
||||
{ "7EUS", 4, 1, &NDS_ARM7.R14_usr },
|
||||
{ "7DSV", 4, 1, &NDS_ARM7.R13_svc },
|
||||
{ "7ESV", 4, 1, &NDS_ARM7.R14_svc },
|
||||
{ "7DAB", 4, 1, &NDS_ARM7.R13_abt },
|
||||
{ "7EAB", 4, 1, &NDS_ARM7.R14_abt },
|
||||
{ "7DUN", 4, 1, &NDS_ARM7.R13_und },
|
||||
{ "7EUN", 4, 1, &NDS_ARM7.R14_und },
|
||||
{ "7DIR", 4, 1, &NDS_ARM7.R13_irq },
|
||||
{ "7EIR", 4, 1, &NDS_ARM7.R14_irq },
|
||||
{ "78FI", 4, 1, &NDS_ARM7.R8_fiq },
|
||||
{ "79FI", 4, 1, &NDS_ARM7.R9_fiq },
|
||||
{ "7AFI", 4, 1, &NDS_ARM7.R10_fiq },
|
||||
{ "7BFI", 4, 1, &NDS_ARM7.R11_fiq },
|
||||
{ "7CFI", 4, 1, &NDS_ARM7.R12_fiq },
|
||||
{ "7DFI", 4, 1, &NDS_ARM7.R13_fiq },
|
||||
{ "7EFI", 4, 1, &NDS_ARM7.R14_fiq },
|
||||
{ "7SVC", 4, 1, &NDS_ARM7.SPSR_svc },
|
||||
{ "7ABT", 4, 1, &NDS_ARM7.SPSR_abt },
|
||||
{ "7UND", 4, 1, &NDS_ARM7.SPSR_und },
|
||||
{ "7IRQ", 4, 1, &NDS_ARM7.SPSR_irq },
|
||||
{ "7FIQ", 4, 1, &NDS_ARM7.SPSR_fiq },
|
||||
{ "7int", 4, 1, &NDS_ARM7.intVector },
|
||||
{ "7LDT", 1, 1, &NDS_ARM7.LDTBit },
|
||||
{ "7Wai", 4, 1, &NDS_ARM7.waitIRQ },
|
||||
{ "7wIR", 4, 1, &NDS_ARM7.wIRQ, },
|
||||
{ "7wir", 4, 1, &NDS_ARM7.wirq, },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
SFORMAT SF_ARM9[]={
|
||||
{ &NDS_ARM9.instruction, 4|SS_RLSB, "9INS" },
|
||||
{ &NDS_ARM9.instruct_adr, 4|SS_RLSB, "9INA" },
|
||||
{ &NDS_ARM9.next_instruction, 4|SS_RLSB, "9INN" },
|
||||
{ NDS_ARM9.R, 4|SS_MULT(16), "9REG" },
|
||||
{ &NDS_ARM9.CPSR, 4|SS_RLSB, "9CPS" },
|
||||
{ &NDS_ARM9.SPSR, 4|SS_RLSB, "9SPS" },
|
||||
{ &NDS_ARM9.R13_usr, 4|SS_RLSB, "9DUS" },
|
||||
{ &NDS_ARM9.R14_usr, 4|SS_RLSB, "9EUS" },
|
||||
{ &NDS_ARM9.R13_svc, 4|SS_RLSB, "9DSV" },
|
||||
{ &NDS_ARM9.R14_svc, 4|SS_RLSB, "9ESV" },
|
||||
{ &NDS_ARM9.R13_abt, 4|SS_RLSB, "9DAB" },
|
||||
{ &NDS_ARM9.R14_abt, 4|SS_RLSB, "9EAB" },
|
||||
{ &NDS_ARM9.R13_und, 4|SS_RLSB, "9DUN" },
|
||||
{ &NDS_ARM9.R14_und, 4|SS_RLSB, "9EUN" },
|
||||
{ &NDS_ARM9.R13_irq, 4|SS_RLSB, "9DIR" },
|
||||
{ &NDS_ARM9.R14_irq, 4|SS_RLSB, "9EIR" },
|
||||
{ &NDS_ARM9.R8_fiq, 4|SS_RLSB, "98FI" },
|
||||
{ &NDS_ARM9.R9_fiq, 4|SS_RLSB, "99FI" },
|
||||
{ &NDS_ARM9.R10_fiq, 4|SS_RLSB, "9AFI" },
|
||||
{ &NDS_ARM9.R11_fiq, 4|SS_RLSB, "9BFI" },
|
||||
{ &NDS_ARM9.R12_fiq, 4|SS_RLSB, "9CFI" },
|
||||
{ &NDS_ARM9.R13_fiq, 4|SS_RLSB, "9DFI" },
|
||||
{ &NDS_ARM9.R14_fiq, 4|SS_RLSB, "9EFI" },
|
||||
{ &NDS_ARM9.SPSR_svc, 4|SS_RLSB, "9SVC" },
|
||||
{ &NDS_ARM9.SPSR_abt, 4|SS_RLSB, "9ABT" },
|
||||
{ &NDS_ARM9.SPSR_und, 4|SS_RLSB, "9UND" },
|
||||
{ &NDS_ARM9.SPSR_irq, 4|SS_RLSB, "9IRQ" },
|
||||
{ &NDS_ARM9.SPSR_fiq, 4|SS_RLSB, "9FIQ" },
|
||||
{ &NDS_ARM9.intVector, 4|SS_RLSB, "9int" },
|
||||
{ &NDS_ARM9.LDTBit, 1, "9LDT" },
|
||||
{ &NDS_ARM9.waitIRQ, 4|SS_RLSB, "9Wai" },
|
||||
{ &NDS_ARM9.wIRQ, 4|SS_RLSB, "9wIR" },
|
||||
{ &NDS_ARM9.wirq, 4|SS_RLSB, "9wir" },
|
||||
{ "9INS", 4, 1, &NDS_ARM9.instruction},
|
||||
{ "9INA", 4, 1, &NDS_ARM9.instruct_adr},
|
||||
{ "9INN", 4, 1, &NDS_ARM9.next_instruction},
|
||||
{ "9REG", 4,16, NDS_ARM9.R},
|
||||
{ "9CPS", 4, 1, &NDS_ARM9.CPSR},
|
||||
{ "9SPS", 4, 1, &NDS_ARM9.SPSR},
|
||||
{ "9DUS", 4, 1, &NDS_ARM9.R13_usr},
|
||||
{ "9EUS", 4, 1, &NDS_ARM9.R14_usr},
|
||||
{ "9DSV", 4, 1, &NDS_ARM9.R13_svc},
|
||||
{ "9ESV", 4, 1, &NDS_ARM9.R14_svc},
|
||||
{ "9DAB", 4, 1, &NDS_ARM9.R13_abt},
|
||||
{ "9EAB", 4, 1, &NDS_ARM9.R14_abt},
|
||||
{ "9DUN", 4, 1, &NDS_ARM9.R13_und},
|
||||
{ "9EUN", 4, 1, &NDS_ARM9.R14_und},
|
||||
{ "9DIR", 4, 1, &NDS_ARM9.R13_irq},
|
||||
{ "9EIR", 4, 1, &NDS_ARM9.R14_irq},
|
||||
{ "98FI", 4, 1, &NDS_ARM9.R8_fiq},
|
||||
{ "99FI", 4, 1, &NDS_ARM9.R9_fiq},
|
||||
{ "9AFI", 4, 1, &NDS_ARM9.R10_fiq},
|
||||
{ "9BFI", 4, 1, &NDS_ARM9.R11_fiq},
|
||||
{ "9CFI", 4, 1, &NDS_ARM9.R12_fiq},
|
||||
{ "9DFI", 4, 1, &NDS_ARM9.R13_fiq},
|
||||
{ "9EFI", 4, 1, &NDS_ARM9.R14_fiq},
|
||||
{ "9SVC", 4, 1, &NDS_ARM9.SPSR_svc},
|
||||
{ "9ABT", 4, 1, &NDS_ARM9.SPSR_abt},
|
||||
{ "9UND", 4, 1, &NDS_ARM9.SPSR_und},
|
||||
{ "9IRQ", 4, 1, &NDS_ARM9.SPSR_irq},
|
||||
{ "9FIQ", 4, 1, &NDS_ARM9.SPSR_fiq},
|
||||
{ "9int", 4, 1, &NDS_ARM9.intVector},
|
||||
{ "9LDT", 1, 1, &NDS_ARM9.LDTBit},
|
||||
{ "9Wai", 4, 1, &NDS_ARM9.waitIRQ},
|
||||
{ "9wIR", 4, 1, &NDS_ARM9.wIRQ},
|
||||
{ "9wir", 4, 1, &NDS_ARM9.wirq},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
SFORMAT SF_MEM[]={
|
||||
{ ARM9Mem.ARM9_ITCM, 0x8000, "ITCM" },
|
||||
{ ARM9Mem.ARM9_DTCM, 0x4000, "DTCM" },
|
||||
{ ARM9Mem.MAIN_MEM, 0x400000, "WRAM" },
|
||||
{ "ITCM", 1, 0x8000, ARM9Mem.ARM9_ITCM},
|
||||
{ "DTCM", 1, 0x4000, ARM9Mem.ARM9_DTCM},
|
||||
{ "WRAM", 1, 0x400000, ARM9Mem.MAIN_MEM},
|
||||
|
||||
//NOTE - this is not as large as the allocated memory.
|
||||
//the memory is overlarge due to the way our memory map system is setup
|
||||
//but there are actually no more registers than this
|
||||
{ ARM9Mem.ARM9_REG, 0x2000, "9REG" },
|
||||
{ "9REG", 1, 0x2000, ARM9Mem.ARM9_REG},
|
||||
|
||||
{ ARM9Mem.ARM9_VMEM, 0x800, "VMEM" },
|
||||
{ ARM9Mem.ARM9_OAM, 0x800, "OAMS" },
|
||||
{ ARM9Mem.ARM9_ABG, 0x80000, "ABGM" },
|
||||
{ ARM9Mem.ARM9_BBG, 0x20000, "BBGM" },
|
||||
{ ARM9Mem.ARM9_AOBJ, 0x40000, "AOBJ" },
|
||||
{ ARM9Mem.ARM9_BOBJ, 0x20000, "BOBJ" },
|
||||
{ ARM9Mem.ARM9_LCD, 0xA4000, "LCDM" },
|
||||
{ MMU.ARM7_ERAM, 0x10000, "ERAM" },
|
||||
{ MMU.ARM7_REG, 0x10000, "7REG" },
|
||||
{ MMU.ARM7_WIRAM, 0x10000, "WIRA" },
|
||||
{ MMU.SWIRAM, 0x8000, "SWIR" },
|
||||
{ MMU.CART_RAM, SRAM_SIZE, "SRAM" },
|
||||
{ "VMEM", 1, 0x800, ARM9Mem.ARM9_VMEM},
|
||||
{ "OAMS", 1, 0x800, ARM9Mem.ARM9_OAM},
|
||||
{ "ABGM", 1, 0x80000, ARM9Mem.ARM9_ABG},
|
||||
{ "BBGM", 1, 0x20000, ARM9Mem.ARM9_BBG},
|
||||
{ "AOBJ", 1, 0x40000, ARM9Mem.ARM9_AOBJ},
|
||||
{ "BOBJ", 1, 0x20000, ARM9Mem.ARM9_BOBJ},
|
||||
{ "LCDM", 1, 0xA4000, ARM9Mem.ARM9_LCD},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
SFORMAT SF_NDS[]={
|
||||
{ &nds.ARM9Cycle, 4|SS_RLSB, "_9CY" },
|
||||
{ &nds.ARM7Cycle, 4|SS_RLSB, "_7CY" },
|
||||
{ &nds.cycles, 4|SS_RLSB, "_CYC" },
|
||||
{ nds.timerCycle, 4|SS_MULT(8), "_TCY" },
|
||||
{ nds.timerOver, 4|SS_MULT(8), "_TOV" },
|
||||
{ &nds.nextHBlank, 4|SS_RLSB, "_NHB" },
|
||||
{ &nds.VCount, 4|SS_RLSB, "_VCT" },
|
||||
{ &nds.old, 4|SS_RLSB, "_OLD" },
|
||||
{ &nds.diff, 4|SS_RLSB, "_DIF" },
|
||||
{ &nds.lignerendu, 4|SS_RLSB, "_LIG" },
|
||||
{ &nds.touchX, 2|SS_RLSB, "_TPX" },
|
||||
{ &nds.touchY, 2|SS_RLSB, "_TPY" },
|
||||
{ "_9CY", 4, 1, &nds.ARM9Cycle},
|
||||
{ "_7CY", 4, 1, &nds.ARM7Cycle},
|
||||
{ "_CYC", 4, 1, &nds.cycles},
|
||||
{ "_TCY", 4, 8, nds.timerCycle},
|
||||
{ "_TOV", 4, 8, nds.timerOver},
|
||||
{ "_NHB", 4, 1, &nds.nextHBlank},
|
||||
{ "_VCT", 4, 1, &nds.VCount},
|
||||
{ "_OLD", 4, 1, &nds.old},
|
||||
{ "_DIF", 4, 1, &nds.diff},
|
||||
{ "_LIG", 4, 1, &nds.lignerendu},
|
||||
{ "_TPX", 2, 1, &nds.touchX},
|
||||
{ "_TPY", 2, 1, &nds.touchY},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
SFORMAT SF_MMU[]={
|
||||
{ "M7BI", 1, 0x4000, MMU.ARM7_BIOS},
|
||||
{ "M7ER", 1, 0x10000, MMU.ARM7_ERAM},
|
||||
{ "M7RG", 1, 0x10000, MMU.ARM7_REG},
|
||||
{ "M7WI", 1, 0x10000, MMU.ARM7_WIRAM},
|
||||
{ "MVRM", 1, 9, MMU.vram_mode},
|
||||
{ "MSWI", 1, 0x8000, MMU.SWIRAM},
|
||||
{ "MCRA", 1, 0x10000, MMU.CART_RAM},
|
||||
{ "M9RW", 1, 1, &MMU.ARM9_RW_MODE},
|
||||
{ "MDTC", 4, 1, &MMU.DTCMRegion},
|
||||
{ "MITC", 4, 1, &MMU.ITCMRegion},
|
||||
{ "MTIM", 2, 8, MMU.timer},
|
||||
{ "MTMO", 4, 8, MMU.timerMODE},
|
||||
{ "MTON", 4, 8, MMU.timerON},
|
||||
{ "MTRN", 4, 8, MMU.timerRUN},
|
||||
{ "MTRL", 2, 8, MMU.timerReload},
|
||||
{ "MIME", 4, 2, MMU.reg_IME},
|
||||
{ "MIE_", 4, 2, MMU.reg_IE},
|
||||
{ "MIF_", 4, 2, MMU.reg_IF},
|
||||
{ "MDST", 4, 8, MMU.DMAStartTime},
|
||||
{ "MDCY", 4, 8, MMU.DMACycle},
|
||||
{ "MDCR", 4, 8, MMU.DMACrt},
|
||||
{ "MDMA", 4, 8, MMU.DMAing},
|
||||
|
||||
//begin memory chips
|
||||
//we are skipping the firmware, because we really don't want to save the firmware to the savestate
|
||||
//but, we will need to think about the philosophy of this.
|
||||
//should we perhaps hash the current firmware and save it, so that we can match it against the loader's firmware?
|
||||
{ "BUCO", 1, 1, &MMU.bupmem.com},
|
||||
{ "BUAD", 4, 1, &MMU.bupmem.addr},
|
||||
{ "BUAS", 1, 1, &MMU.bupmem.addr_shift},
|
||||
{ "BUAZ", 1, 1, &MMU.bupmem.addr_size},
|
||||
{ "BUWE", 4, 1, &MMU.bupmem.write_enable},
|
||||
//writeable_buffer ???
|
||||
//end memory chips
|
||||
|
||||
{ "MC0A", 4, 1, &MMU.dscard[0].address},
|
||||
{ "MC0T", 4, 1, &MMU.dscard[0].transfer_count},
|
||||
{ "MC1A", 4, 1, &MMU.dscard[1].address},
|
||||
{ "MC1T", 4, 1, &MMU.dscard[1].transfer_count},
|
||||
{ "MCHT", 4, 1, &MMU.CheckTimers},
|
||||
{ "MCHD", 4, 1, &MMU.CheckDMAs},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
||||
void mmu_savestate(std::ostream* os)
|
||||
{
|
||||
//version
|
||||
write32le(0,os);
|
||||
|
||||
write32le(MMU.bupmem.size,os);
|
||||
os->write((char*)MMU.bupmem.data,MMU.bupmem.size);
|
||||
}
|
||||
|
||||
bool mmu_loadstate(std::istream* is)
|
||||
{
|
||||
//read version
|
||||
int version;
|
||||
if(read32le(&version,is) != 1) return false;
|
||||
if(version != 0) return false;
|
||||
|
||||
u32 bupmem_size;
|
||||
if(read32le(&bupmem_size,is) != 1) return false;
|
||||
if(bupmem_size != MMU.bupmem.size) return false; //mismatch between current initialized and saved size
|
||||
|
||||
is->read((char*)MMU.bupmem.data,bupmem_size);
|
||||
if(is->fail()) return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/* Format time and convert to string */
|
||||
char * format_time(time_t cal_time)
|
||||
{
|
||||
|
|
@ -281,27 +349,28 @@ int sram_save (const char *file_name) {
|
|||
|
||||
}
|
||||
|
||||
static SFORMAT *CheckS(SFORMAT *sf, u32 tsize, char *desc)
|
||||
static SFORMAT *CheckS(SFORMAT *sf, u32 size, u32 count, char *desc)
|
||||
{
|
||||
while(sf->v)
|
||||
{
|
||||
if(sf->s==~0) // Link to another SFORMAT structure.
|
||||
{
|
||||
SFORMAT *tmp;
|
||||
if((tmp= CheckS((SFORMAT *)sf->v, tsize, desc) ))
|
||||
return(tmp);
|
||||
sf++;
|
||||
continue;
|
||||
}
|
||||
//NOT SUPPORTED RIGHT NOW
|
||||
//if(sf->size==~0) // Link to another SFORMAT structure.
|
||||
//{
|
||||
// SFORMAT *tmp;
|
||||
// if((tmp= CheckS((SFORMAT *)sf->v, tsize, desc) ))
|
||||
// return(tmp);
|
||||
// sf++;
|
||||
// continue;
|
||||
//}
|
||||
if(!memcmp(desc,sf->desc,4))
|
||||
{
|
||||
if(tsize!=(sf->s))
|
||||
return(0);
|
||||
return(sf);
|
||||
if(sf->size != size || sf->count != count)
|
||||
return 0;
|
||||
return sf;
|
||||
}
|
||||
sf++;
|
||||
}
|
||||
return(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -312,34 +381,31 @@ static bool ReadStateChunk(std::istream* is, SFORMAT *sf, int size)
|
|||
|
||||
while(is->tellg()<temp+size)
|
||||
{
|
||||
u32 tsize;
|
||||
u32 size, count;
|
||||
|
||||
char toa[4];
|
||||
is->read(toa,4);
|
||||
if(is->fail())
|
||||
return false;
|
||||
|
||||
read32le(&tsize,is);
|
||||
int count = SS_UNMULT(tsize);
|
||||
int size = tsize & ~SS_FLAGS;
|
||||
bool rlsb = (count!=0);
|
||||
if(!read32le(&size,is)) return false;
|
||||
if(!read32le(&count,is)) return false;
|
||||
|
||||
if((tmp=CheckS(sf,tsize,toa)))
|
||||
if((tmp=CheckS(sf,size,count,toa)))
|
||||
{
|
||||
|
||||
|
||||
if(count == 0) count=1;
|
||||
|
||||
for(int i=0;i<count;i++) {
|
||||
|
||||
if(tmp->s&SS_INDIRECT)
|
||||
is->read(*(char **)tmp->v,size);
|
||||
else
|
||||
if(size == 1) {
|
||||
//special case: read a huge byte array
|
||||
is->read((char *)tmp->v,count);
|
||||
} else {
|
||||
for(int i=0;i<count;i++)
|
||||
{
|
||||
is->read((char *)tmp->v + i*size,size);
|
||||
|
||||
#ifndef LOCAL_LE
|
||||
if(rlsb)
|
||||
FlipByteOrder((u8*)tmp->v + i*size,size);
|
||||
#endif
|
||||
#ifndef LOCAL_LE
|
||||
if(rlsb)
|
||||
FlipByteOrder((u8*)tmp->v + i*size,size);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -356,50 +422,49 @@ static int SubWrite(std::ostream* os, SFORMAT *sf)
|
|||
|
||||
while(sf->v)
|
||||
{
|
||||
if(sf->s==~0) //Link to another struct
|
||||
{
|
||||
uint32 tmp;
|
||||
//not supported right now
|
||||
//if(sf->size==~0) //Link to another struct
|
||||
//{
|
||||
// uint32 tmp;
|
||||
|
||||
if(!(tmp=SubWrite(os,(SFORMAT *)sf->v)))
|
||||
return(0);
|
||||
acc+=tmp;
|
||||
sf++;
|
||||
continue;
|
||||
}
|
||||
// if(!(tmp=SubWrite(os,(SFORMAT *)sf->v)))
|
||||
// return(0);
|
||||
// acc+=tmp;
|
||||
// sf++;
|
||||
// continue;
|
||||
//}
|
||||
|
||||
int count = SS_UNMULT(sf->s);
|
||||
int size = sf->s & ~SS_FLAGS;
|
||||
bool rlsb = (count!=0);
|
||||
int count = sf->count;
|
||||
int size = sf->size;
|
||||
|
||||
acc+=8; //Description + size
|
||||
|
||||
if(count==0) count=1;
|
||||
acc+=12; //Description + size + count
|
||||
|
||||
acc += count * size;
|
||||
|
||||
if(os) //Are we writing or calculating the size of this block?
|
||||
{
|
||||
os->write(sf->desc,4);
|
||||
write32le(sf->s,os);
|
||||
write32le(sf->size,os);
|
||||
write32le(sf->count,os);
|
||||
|
||||
for(int i=0;i<count;i++) {
|
||||
if(size == 1) {
|
||||
//special case: write a huge byte array
|
||||
os->write((char *)sf->v,count);
|
||||
} else {
|
||||
for(int i=0;i<count;i++) {
|
||||
|
||||
#ifndef LOCAL_LE
|
||||
if(rlsb)
|
||||
#ifndef LOCAL_LE
|
||||
FlipByteOrder((u8*)sf->v,sf->s&(~SS_FLAGS));
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if(sf->s&SS_INDIRECT)
|
||||
os->write(*(char **)sf->v,size);
|
||||
else
|
||||
os->write((char*)sf->v + i*size,size);
|
||||
|
||||
//Now restore the original byte order.
|
||||
#ifndef LOCAL_LE
|
||||
if(rlsb)
|
||||
FlipByteOrder((u8*)sf->v,sf->s&(~SS_FLAGS));
|
||||
#endif
|
||||
|
||||
//Now restore the original byte order.
|
||||
#ifndef LOCAL_LE
|
||||
if(rlsb)
|
||||
FlipByteOrder((u8*)sf->v,sf->s&(~SS_FLAGS));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
sf++;
|
||||
|
|
@ -508,10 +573,12 @@ static void writechunks(std::ostream* os) {
|
|||
savestate_WriteChunk(os,2,SF_ARM7);
|
||||
savestate_WriteChunk(os,3,SF_MEM);
|
||||
savestate_WriteChunk(os,4,SF_NDS);
|
||||
savestate_WriteChunk(os,5,gpu_savestate);
|
||||
savestate_WriteChunk(os,50,SF_MMU);
|
||||
savestate_WriteChunk(os,51,mmu_savestate);
|
||||
savestate_WriteChunk(os,6,gpu_savestate);
|
||||
savestate_WriteChunk(os,7,spu_savestate);
|
||||
savestate_WriteChunk(os,60,SF_GFX3D);
|
||||
savestate_WriteChunk(os,61,gfx3d_savestate);
|
||||
savestate_WriteChunk(os,80,SF_GFX3D);
|
||||
savestate_WriteChunk(os,81,gfx3d_savestate);
|
||||
savestate_WriteChunk(os,0xFFFFFFFF,(SFORMAT*)0);
|
||||
}
|
||||
|
||||
|
|
@ -531,10 +598,12 @@ static bool ReadStateChunks(std::istream* is, s32 totalsize)
|
|||
case 2: if(!ReadStateChunk(is,SF_ARM7,size)) ret=false; break;
|
||||
case 3: if(!ReadStateChunk(is,SF_MEM,size)) ret=false; break;
|
||||
case 4: if(!ReadStateChunk(is,SF_NDS,size)) ret=false; break;
|
||||
case 5: if(!gpu_loadstate(is)) ret=false; break;
|
||||
case 50: if(!ReadStateChunk(is,SF_MMU,size)) ret=false; break;
|
||||
case 51: if(!mmu_loadstate(is)) ret=false; break;
|
||||
case 6: if(!gpu_loadstate(is)) ret=false; break;
|
||||
case 7: if(!spu_loadstate(is)) ret=false; break;
|
||||
case 60: if(!ReadStateChunk(is,SF_GFX3D,size)) ret=false; break;
|
||||
case 61: if(!gfx3d_loadstate(is)) ret=false; break;
|
||||
case 80: if(!ReadStateChunk(is,SF_GFX3D,size)) ret=false; break;
|
||||
case 81: if(!gfx3d_loadstate(is)) ret=false; break;
|
||||
default:
|
||||
ret=false;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -36,32 +36,19 @@ typedef struct
|
|||
|
||||
struct SFORMAT
|
||||
{
|
||||
//a void* to the data or a void** to the data
|
||||
void *v;
|
||||
|
||||
//size, plus flags
|
||||
uint32 s;
|
||||
|
||||
//a string description of the element
|
||||
char *desc;
|
||||
|
||||
//the size of each element
|
||||
u32 size;
|
||||
|
||||
//the number of each element
|
||||
u32 count;
|
||||
|
||||
//a void* to the data or a void** to the data
|
||||
void *v;
|
||||
};
|
||||
|
||||
//X multiple multibyte elements
|
||||
#define SS_MULT(X) (X<<24)
|
||||
|
||||
//indicates that the value is a multibyte integer that needs to be put in the correct byte order
|
||||
//this is the same as SS_MULT(1)
|
||||
#define SS_RLSB SS_MULT(1)
|
||||
|
||||
|
||||
|
||||
//all flags together so that we can mask them out and get the size
|
||||
#define SS_FLAGS (SS_INDIRECT|SS_MULT(127))
|
||||
|
||||
//extract the multiplier
|
||||
#define SS_UNMULT(X) ((X>>24)&0x7F)
|
||||
|
||||
|
||||
extern savestates_t savestates[NB_STATES];
|
||||
|
||||
void clear_savestates();
|
||||
|
|
|
|||
Loading…
Reference in New Issue