more fixes to vram mapping. this time, for one particular test case, gpu accesses to unmapped memory return 0 like it is supposed to. I will wait for more test cases before I change it in other places.
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@ -11,7 +11,7 @@ struct ALIGN(16) ARM9_struct {
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u8 ARM9_REG[0x1000000];
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u8 ARM9_BIOS[0x8000];
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u8 ARM9_VMEM[0x800];
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u8 ARM9_LCD[0xA4000];
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u8 ARM9_LCD[0xA4000+0x4000]; //an extra 16KB for blank memory
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u8 ARM9_OAM[0x800];
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u8* ExtPal[2][4];
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@ -1592,8 +1592,9 @@ INLINE void renderline_textBG(GPU * gpu, u16 XBG, u16 YBG, u16 LG)
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u16 wmask = (lg-1);
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u16 hmask = (ht-1);
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u16 tmp = ((YBG & hmask) >> 3);
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u8 *map = NULL;
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u8 *tile, *pal, *line;
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u32 map;
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u8 *pal, *line;
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u32 tile;
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u16 color;
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u16 xoff;
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u16 yoff;
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@ -1601,18 +1602,19 @@ INLINE void renderline_textBG(GPU * gpu, u16 XBG, u16 YBG, u16 LG)
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u16 xfin;
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s8 line_dir = 1;
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u8 * mapinfo;
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u32 mapinfo;
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TILEENTRY tileentry;
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u32 tmp_map = gpu->BG_map_ram[num] + (tmp&31) * 64;
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if(tmp>31)
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tmp_map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ;
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map = (u8*)MMU_RenderMapToLCD(tmp_map);
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if(!map) return; // no map
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//map = (u8*)MMU_RenderMapToLCD(tmp_map);
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map = tmp_map;
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//if(!map) return; // no map
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tile = (u8*) MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
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if(!tile) return; // no tiles
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tile = gpu->BG_tile_ram[num];
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//if(!tile) return; // no tiles
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xoff = XBG;
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pal = ARM9Mem.ARM9_VMEM + gpu->core * ADDRESS_STEP_1KB;
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@ -1627,11 +1629,11 @@ INLINE void renderline_textBG(GPU * gpu, u16 XBG, u16 YBG, u16 LG)
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tmp = ((xoff&wmask)>>3);
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mapinfo = map + (tmp&0x1F) * 2;
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if(tmp>31) mapinfo += 32*32*2;
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tileentry.val = T1ReadWord(mapinfo, 0);
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tileentry.val = T1ReadWord(MMU_gpu_map(mapinfo), 0);
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tilePalette = (tileentry.bits.Palette*16);
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line = (u8 * )tile + (tileentry.bits.TileNum * 0x20) + ((tileentry.bits.VFlip) ? (7*4)-yoff : yoff);
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line = (u8*)MMU_gpu_map(tile + (tileentry.bits.TileNum * 0x20) + ((tileentry.bits.VFlip) ? (7*4)-yoff : yoff));
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if(tileentry.bits.HFlip)
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{
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@ -1690,9 +1692,9 @@ INLINE void renderline_textBG(GPU * gpu, u16 XBG, u16 YBG, u16 LG)
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tmp = (xoff & (lg-1))>>3;
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mapinfo = map + (tmp & 31) * 2;
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if(tmp > 31) mapinfo += 32*32*2;
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tileentry.val = T1ReadWord(mapinfo, 0);
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tileentry.val = T1ReadWord(MMU_gpu_map(mapinfo), 0);
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line = (u8 * )tile + (tileentry.bits.TileNum*0x40) + ((tileentry.bits.VFlip) ? (7*8)-yoff : yoff);
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line = (u8*)MMU_gpu_map(tile + (tileentry.bits.TileNum*0x40) + ((tileentry.bits.VFlip) ? (7*8)-yoff : yoff));
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if(tileentry.bits.HFlip)
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{
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@ -420,6 +420,25 @@ u8 *MMU_RenderMapToLCD(u32 vram_addr)
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}
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FORCEINLINE void* MMU_gpu_map(u32 vram_addr)
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{
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//THIS FUNCTION IS NOT AS DANGEROUS!
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//as an alternative to the above, use this:
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//it is supposed to map a single gpu vram address to emulator host memory
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//but it returns a pointer to some zero memory in case of accesses to unmapped memory.
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//this correctly handles the case with tile accesses to unmapped memory.
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//it could also potentially go through a different LUT than vram_arm9_map in case we discover
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//that it needs to be set up with different or no mirroring
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//(I think it is a reasonable possibility that only the cpu has the nutty mirroring rules)
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u32 vram_page = (vram_addr>>14)&(VRAM_ARM9_PAGES-1);
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u32 ofs = vram_addr & 0x3FFF;
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vram_page = vram_arm9_map[vram_page];
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//blank pages are handled by the extra 16KB of blank memory at the end of ARM9_LCD
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//and the fact that blank pages are mapped to appear at that location
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return ARM9Mem.ARM9_LCD + (vram_page<<14) + ofs;
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}
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template<u8 DMA_CHANNEL>
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void DMAtoVRAMmapping()
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{
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@ -181,6 +181,7 @@ extern struct armcpu_memory_iface arm7_base_memory_iface;
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extern struct armcpu_memory_iface arm9_direct_memory_iface;
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extern u8 *MMU_RenderMapToLCD(u32 vram_addr);
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extern void* MMU_gpu_map(u32 vram_addr);
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enum MMU_ACCESS_TYPE
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{
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@ -31,12 +31,12 @@ static INLINE u8 T1ReadByte(u8 * mem, u32 addr)
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return mem[addr];
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}
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static INLINE u16 T1ReadWord(u8 * mem, u32 addr)
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static INLINE u16 T1ReadWord(void * mem, u32 addr)
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{
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#ifdef WORDS_BIGENDIAN
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return (mem[addr + 1] << 8) | mem[addr];
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#else
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return *((u16 *) (mem + addr));
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return *((u16 *) ((u8*)mem + addr));
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#endif
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}
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