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desmume
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Added the ability to write to the external firmware image (when there's one). 

The firmware can now save new settings!
This commit is contained in:
luigi__ 2009-03-10 16:48:03 +00:00
parent fabcf94d50
commit 5f617ca6ef
2 changed files with 175 additions and 175 deletions
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142
desmume/src/NDSSystem.cpp
View File

@ -852,10 +852,70 @@ void NDS_Reset( void)
MMU_clearMem();
//ARM7 BIOS IRQ HANDLER
if(CommonSettings.UseExtBIOS == true)
inf = fopen(CommonSettings.ARM7BIOS,"rb");
else
inf = NULL;
if(inf) {
fread(MMU.ARM7_BIOS,1,16384,inf);
fclose(inf);
if(CommonSettings.SWIFromBIOS == true) NDS_ARM7.swi_tab = 0;
else NDS_ARM7.swi_tab = ARM7_swi_tab;
INFO("ARM7 BIOS is loaded.\n");
} else {
NDS_ARM7.swi_tab = ARM7_swi_tab;
_MMU_write32<ARMCPU_ARM7>(0x00, 0xE25EF002);
_MMU_write32<ARMCPU_ARM7>(0x04, 0xEAFFFFFE);
_MMU_write32<ARMCPU_ARM7>(0x18, 0xEA000000);
_MMU_write32<ARMCPU_ARM7>(0x20, 0xE92D500F);
_MMU_write32<ARMCPU_ARM7>(0x24, 0xE3A00301);
_MMU_write32<ARMCPU_ARM7>(0x28, 0xE28FE000);
_MMU_write32<ARMCPU_ARM7>(0x2C, 0xE510F004);
_MMU_write32<ARMCPU_ARM7>(0x30, 0xE8BD500F);
_MMU_write32<ARMCPU_ARM7>(0x34, 0xE25EF004);
}
//ARM9 BIOS IRQ HANDLER
if(CommonSettings.UseExtBIOS == true)
inf = fopen(CommonSettings.ARM9BIOS,"rb");
else
inf = NULL;
//memcpy(ARM9Mem.ARM9_BIOS + 0x20, gba_header_data_0x04, 156);
if(inf) {
fread(ARM9Mem.ARM9_BIOS,1,4096,inf);
fclose(inf);
if(CommonSettings.SWIFromBIOS == true) NDS_ARM9.swi_tab = 0;
else NDS_ARM9.swi_tab = ARM9_swi_tab;
INFO("ARM9 BIOS is loaded.\n");
} else {
NDS_ARM9.swi_tab = ARM9_swi_tab;
_MMU_write32<ARMCPU_ARM9>(0xFFFF0018, 0xEA000000);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0020, 0xE92D500F);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0024, 0xEE190F11);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0028, 0xE1A00620);
_MMU_write32<ARMCPU_ARM9>(0xFFFF002C, 0xE1A00600);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0030, 0xE2800C40);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0034, 0xE28FE000);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0038, 0xE510F004);
_MMU_write32<ARMCPU_ARM9>(0xFFFF003C, 0xE8BD500F);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0040, 0xE25EF004);
}
/* Is it really needed ??? */
_MMU_write32<ARMCPU_ARM9>(0x0000004, 0xE3A0010E);
_MMU_write32<ARMCPU_ARM9>(0x0000008, 0xE3A01020);
// _MMU_write32<ARMCPU_ARM9>(0x000000C, 0xE1B02110);
_MMU_write32<ARMCPU_ARM9>(0x000000C, 0xE1B02040);
_MMU_write32<ARMCPU_ARM9>(0x0000010, 0xE3B02020);
// _MMU_write32<ARMCPU_ARM9>(0x0000010, 0xE2100202);
if(CommonSettings.UseExtFirmware == true)
NDS_LoadFirmware(CommonSettings.Firmware);
if((CommonSettings.UseExtFirmware == true) && (CommonSettings.BootFromFirmware == true) && (fw_success == TRUE))
if((CommonSettings.UseExtBIOS == true) && (CommonSettings.UseExtFirmware == true) && (CommonSettings.BootFromFirmware == true) && (fw_success == TRUE))
{
for(i = 0; i < nds.FW_ARM9BootCodeSize; i += 4)
{
@ -869,6 +929,8 @@ void NDS_Reset( void)
armcpu_init(&NDS_ARM9, nds.FW_ARM9BootCodeAddr);
armcpu_init(&NDS_ARM7, nds.FW_ARM7BootCodeAddr);
//armcpu_init(&NDS_ARM9, 0xFFFF0000);
//armcpu_init(&NDS_ARM7, 0x00000000);
}
else
{
@ -940,68 +1002,6 @@ void NDS_Reset( void)
//_MMU_write32[ARMCPU_ARM9](0x02007FFC, 0xE92D4030);
//ARM7 BIOS IRQ HANDLER
if(CommonSettings.UseExtBIOS == true)
inf = fopen(CommonSettings.ARM7BIOS,"rb");
else
inf = NULL;
if(inf) {
fread(MMU.ARM7_BIOS,1,16384,inf);
fclose(inf);
if(CommonSettings.SWIFromBIOS == true) NDS_ARM7.swi_tab = 0;
else NDS_ARM7.swi_tab = ARM7_swi_tab;
INFO("ARM7 BIOS is loaded.\n");
} else {
NDS_ARM7.swi_tab = ARM7_swi_tab;
_MMU_write32<ARMCPU_ARM7>(0x00, 0xE25EF002);
_MMU_write32<ARMCPU_ARM7>(0x04, 0xEAFFFFFE);
_MMU_write32<ARMCPU_ARM7>(0x18, 0xEA000000);
_MMU_write32<ARMCPU_ARM7>(0x20, 0xE92D500F);
_MMU_write32<ARMCPU_ARM7>(0x24, 0xE3A00301);
_MMU_write32<ARMCPU_ARM7>(0x28, 0xE28FE000);
_MMU_write32<ARMCPU_ARM7>(0x2C, 0xE510F004);
_MMU_write32<ARMCPU_ARM7>(0x30, 0xE8BD500F);
_MMU_write32<ARMCPU_ARM7>(0x34, 0xE25EF004);
}
//ARM9 BIOS IRQ HANDLER
if(CommonSettings.UseExtBIOS == true)
inf = fopen(CommonSettings.ARM9BIOS,"rb");
else
inf = NULL;
//memcpy(ARM9Mem.ARM9_BIOS + 0x20, gba_header_data_0x04, 156);
if(inf) {
fread(ARM9Mem.ARM9_BIOS,1,4096,inf);
fclose(inf);
if(CommonSettings.SWIFromBIOS == true) NDS_ARM9.swi_tab = 0;
else NDS_ARM9.swi_tab = ARM9_swi_tab;
INFO("ARM9 BIOS is loaded.\n");
} else {
NDS_ARM9.swi_tab = ARM9_swi_tab;
_MMU_write32<ARMCPU_ARM9>(0xFFFF0018, 0xEA000000);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0020, 0xE92D500F);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0024, 0xEE190F11);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0028, 0xE1A00620);
_MMU_write32<ARMCPU_ARM9>(0xFFFF002C, 0xE1A00600);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0030, 0xE2800C40);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0034, 0xE28FE000);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0038, 0xE510F004);
_MMU_write32<ARMCPU_ARM9>(0xFFFF003C, 0xE8BD500F);
_MMU_write32<ARMCPU_ARM9>(0xFFFF0040, 0xE25EF004);
}
_MMU_write32<ARMCPU_ARM9>(0x0000004, 0xE3A0010E);
_MMU_write32<ARMCPU_ARM9>(0x0000008, 0xE3A01020);
// _MMU_write32<ARMCPU_ARM9>(0x000000C, 0xE1B02110);
_MMU_write32<ARMCPU_ARM9>(0x000000C, 0xE1B02040);
_MMU_write32<ARMCPU_ARM9>(0x0000010, 0xE3B02020);
// _MMU_write32<ARMCPU_ARM9>(0x0000010, 0xE2100202);
delete header;
GPU_Reset(MainScreen.gpu, 0);
@ -1346,24 +1346,24 @@ int NDS_LoadFirmware(const char *filename)
{
int i;
unsigned long size;
FILE *file;
//FILE *file;
if ((file = fopen(filename, "rb")) == NULL)
if ((MMU.fw.fp = fopen(filename, "rb+")) == NULL)
return -1;
fseek(file, 0, SEEK_END);
size = ftell(file);
fseek(file, 0, SEEK_SET);
fseek(MMU.fw.fp, 0, SEEK_END);
size = ftell(MMU.fw.fp);
fseek(MMU.fw.fp, 0, SEEK_SET);
if(size > MMU.fw.size)
{
fclose(file);
fclose(MMU.fw.fp);
fw_success = FALSE;
return -1;
}
i = fread(MMU.fw.data, size, 1, file);
fclose(file);
i = fread(MMU.fw.data, size, 1, MMU.fw.fp);
//fclose(file);
INFO("Firmware: decrypting NDS firmware %s...\n", filename);

208
desmume/src/mc.cpp
View File

@ -179,7 +179,7 @@ void mc_reset_com(memory_chip_t *mc)
if ((mc->fp = fopen(mc->filename, "wb+")) != NULL)
elems_written += fwrite((void *)mc->data, 1, mc->size, mc->fp);
}
else if (mc->com == BM_CMD_WRITELOW)
else if ((mc->com == BM_CMD_WRITELOW) || (mc->com == FW_CMD_PAGEWRITE))
{
if (mc->fp)
{
@ -296,39 +296,39 @@ int mc_load_duc(memory_chip_t *mc, const char* filename)
u8 fw_transfer(memory_chip_t *mc, u8 data)
{
if(mc->com == FW_CMD_READ || mc->com == FW_CMD_PAGEWRITE) /* check if we are in a command that needs 3 bytes address */
if(mc->com == FW_CMD_READ || mc->com == FW_CMD_PAGEWRITE) /* check if we are in a command that needs 3 bytes address */
{
if(mc->addr_shift > 0) /* if we got a complete address */
if(mc->addr_shift > 0) /* if we got a complete address */
{
mc->addr_shift--;
mc->addr |= data << (mc->addr_shift * 8); /* argument is a byte of address */
mc->addr_shift--;
mc->addr |= data << (mc->addr_shift * 8); /* argument is a byte of address */
}
else /* if we have received 3 bytes of address, proceed command */
else /* if we have received 3 bytes of address, proceed command */
{
switch(mc->com)
switch(mc->com)
{
case FW_CMD_READ:
if(mc->addr < mc->size) /* check if we can read */
case FW_CMD_READ:
if(mc->addr < mc->size) /* check if we can read */
{
data = mc->data[mc->addr]; /* return byte */
mc->addr++; /* then increment address */
data = mc->data[mc->addr]; /* return byte */
mc->addr++; /* then increment address */
}
break;
case FW_CMD_PAGEWRITE:
if(mc->addr < mc->size)
case FW_CMD_PAGEWRITE:
if(mc->addr < mc->size)
{
mc->data[mc->addr] = data; /* write byte */
mc->addr++;
mc->data[mc->addr] = data; /* write byte */
mc->addr++;
}
break;
}
}
}
else if(mc->com == FW_CMD_READSTATUS)
else if(mc->com == FW_CMD_READSTATUS)
{
return 0;
return (mc->write_enable ? 0x02 : 0x00);
}
else /* finally, check if it's a new command */
{
@ -336,36 +336,36 @@ u8 fw_transfer(memory_chip_t *mc, u8 data)
{
case 0: break; /* nothing */
case FW_CMD_READ: /* read command */
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_READ;
case FW_CMD_READ: /* read command */
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_READ;
break;
case FW_CMD_WRITEENABLE: /* enable writing */
if(mc->writeable_buffer) { mc->write_enable = TRUE; }
case FW_CMD_WRITEENABLE: /* enable writing */
if(mc->writeable_buffer) { mc->write_enable = TRUE; }
break;
case FW_CMD_WRITEDISABLE: /* disable writing */
mc->write_enable = FALSE;
case FW_CMD_WRITEDISABLE: /* disable writing */
mc->write_enable = FALSE;
break;
case FW_CMD_PAGEWRITE: /* write command */
if(mc->write_enable)
case FW_CMD_PAGEWRITE: /* write command */
if(mc->write_enable)
{
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_PAGEWRITE;
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_PAGEWRITE;
}
else { data = 0; }
break;
case FW_CMD_READSTATUS: /* status register command */
mc->com = FW_CMD_READSTATUS;
case FW_CMD_READSTATUS: /* status register command */
mc->com = FW_CMD_READSTATUS;
break;
default:
LOG("Unhandled FW command: %02X\n", data);
LOG("Unhandled FW command: %02X\n", data);
break;
}
}
@ -375,49 +375,49 @@ u8 fw_transfer(memory_chip_t *mc, u8 data)
u8 bm_transfer(memory_chip_t *mc, u8 data)
{
if(mc->com == BM_CMD_READLOW || mc->com == BM_CMD_WRITELOW) /* check if we are in a command that needs multiple byte address */
if(mc->com == BM_CMD_READLOW || mc->com == BM_CMD_WRITELOW) /* check if we are in a command that needs multiple byte address */
{
if(mc->addr_shift > 0) /* if we got a complete address */
if(mc->addr_shift > 0) /* if we got a complete address */
{
mc->addr_shift--;
mc->addr |= data << (mc->addr_shift * 8); /* argument is a byte of address */
mc->addr_shift--;
mc->addr |= data << (mc->addr_shift * 8); /* argument is a byte of address */
}
else /* if we have received all bytes of address, proceed command */
else /* if we have received all bytes of address, proceed command */
{
switch(mc->com)
switch(mc->com)
{
case BM_CMD_READLOW:
if(mc->addr < mc->size) /* check if we can read */
{
//LOG("Read Backup Memory addr %08X(%02X)\n", mc->addr, mc->data[mc->addr]);
data = mc->data[mc->addr]; /* return byte */
mc->addr++; /* then increment address */
}
case BM_CMD_READLOW:
if(mc->addr < mc->size) /* check if we can read */
{
//LOG("Read Backup Memory addr %08X(%02X)\n", mc->addr, mc->data[mc->addr]);
data = mc->data[mc->addr]; /* return byte */
mc->addr++; /* then increment address */
}
break;
case BM_CMD_WRITELOW:
if(mc->addr < mc->size)
{
//LOG("Write Backup Memory addr %08X with %02X\n", mc->addr, data);
mc->data[mc->addr] = data; /* write byte */
mc->addr++;
}
case BM_CMD_WRITELOW:
if(mc->addr < mc->size)
{
//LOG("Write Backup Memory addr %08X with %02X\n", mc->addr, data);
mc->data[mc->addr] = data; /* write byte */
mc->addr++;
}
break;
}
}
}
else if(mc->com == BM_CMD_AUTODETECT)
{
// Store everything in a temporary
mc->autodetectbuf[mc->autodetectsize] = data;
mc->autodetectsize++;
return 0;
}
else if(mc->com == BM_CMD_READSTATUS)
else if(mc->com == BM_CMD_AUTODETECT)
{
//LOG("Backup Memory Read Status: %02X\n", mc->write_enable << 1);
return (mc->write_enable << 1);
// Store everything in a temporary
mc->autodetectbuf[mc->autodetectsize] = data;
mc->autodetectsize++;
return 0;
}
else if(mc->com == BM_CMD_READSTATUS)
{
//LOG("Backup Memory Read Status: %02X\n", mc->write_enable << 1);
return (mc->write_enable << 1);
}
else /* finally, check if it's a new command */
{
@ -425,71 +425,71 @@ u8 bm_transfer(memory_chip_t *mc, u8 data)
{
case 0: break; /* nothing */
case BM_CMD_WRITELOW: /* write command */
if(mc->write_enable)
case BM_CMD_WRITELOW: /* write command */
if(mc->write_enable)
{
if(mc->type == MC_TYPE_AUTODETECT)
{
mc->com = BM_CMD_AUTODETECT;
break;
}
if(mc->type == MC_TYPE_AUTODETECT)
{
mc->com = BM_CMD_AUTODETECT;
break;
}
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_WRITELOW;
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_WRITELOW;
}
else { data = 0; }
break;
case BM_CMD_READLOW: /* read command */
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_READLOW;
case BM_CMD_READLOW: /* read command */
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_READLOW;
break;
case BM_CMD_WRITEDISABLE: /* disable writing */
mc->write_enable = FALSE;
case BM_CMD_WRITEDISABLE: /* disable writing */
mc->write_enable = FALSE;
break;
case BM_CMD_READSTATUS: /* status register command */
mc->com = BM_CMD_READSTATUS;
case BM_CMD_READSTATUS: /* status register command */
mc->com = BM_CMD_READSTATUS;
break;
case BM_CMD_WRITEENABLE: /* enable writing */
if(mc->writeable_buffer) { mc->write_enable = TRUE; }
case BM_CMD_WRITEENABLE: /* enable writing */
if(mc->writeable_buffer) { mc->write_enable = TRUE; }
break;
case BM_CMD_WRITEHIGH: /* write command that's only available on ST M95040-W that I know of */
if(mc->write_enable)
case BM_CMD_WRITEHIGH: /* write command that's only available on ST M95040-W that I know of */
if(mc->write_enable)
{
if(mc->type == MC_TYPE_AUTODETECT)
{
mc->com = BM_CMD_AUTODETECT;
break;
}
if(mc->type == MC_TYPE_AUTODETECT)
{
mc->com = BM_CMD_AUTODETECT;
break;
}
if (mc->type == MC_TYPE_EEPROM1)
mc->addr = 0x100;
else
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_WRITELOW;
if (mc->type == MC_TYPE_EEPROM1)
mc->addr = 0x100;
else
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_WRITELOW;
}
else { data = 0; }
break;
case BM_CMD_READHIGH: /* read command that's only available on ST M95040-W that I know of */
if (mc->type == MC_TYPE_EEPROM1)
mc->addr = 0x100;
else
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_READLOW;
case BM_CMD_READHIGH: /* read command that's only available on ST M95040-W that I know of */
if (mc->type == MC_TYPE_EEPROM1)
mc->addr = 0x100;
else
mc->addr = 0;
mc->addr_shift = mc->addr_size;
mc->com = BM_CMD_READLOW;
break;
default:
LOG("Unhandled Backup Memory command: %02X\n", data);
LOG("Unhandled Backup Memory command: %02X\n", data);
break;
}
}