GPU: Change how DISPCAPCNT's CaptureEnable flag is handled, fixing a graphical issue when starting a battle in Pokemon Black/White. (Regression from r5259.)
- To note: This fix to Pokemon Black/White does not require CommonSettings.pokehax to be enabled. - The CaptureEnable flag is now only read at the start of line 0, instead of being read directly from the DISPCAPCNT register per line. In addition, this same state is held all the way through line 192. - The CaptureEnable flag is now reset at the start of line 192, instead of near the end of line 191 H-blank. (This is the proper behavior according to GBATEK.) - The CaptureEnable flag is now only reset when the VRAM configuration is LCDC, instead of always being reset. This makes it possible for this flag to remain set on line 192 if the VRAM configuration is changed to a non-LCDC configuration. - CommonSettings.pokehax is now initialized to false. - Fix a small bug when setting CommonSettings.pokehax via the command line.
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@ -5122,6 +5122,7 @@ void GPUEngineA::Reset()
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this->_Reset_Base();
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memset(&this->_dispCapCnt, 0, sizeof(DISPCAPCNT_parsed));
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this->_displayCaptureEnable = false;
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this->_BGLayer[GPULayerID_BG0].BMPAddress = MMU_ABG;
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this->_BGLayer[GPULayerID_BG1].BMPAddress = MMU_ABG;
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@ -5253,7 +5254,22 @@ bool GPUEngineA::WillCapture3DLayerDirect(const size_t l)
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bool GPUEngineA::WillDisplayCapture(const size_t l)
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{
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const IOREG_DISPCAPCNT &DISPCAPCNT = this->_IORegisterMap->DISPCAPCNT;
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return (DISPCAPCNT.CaptureEnable != 0) && (vramConfiguration.banks[DISPCAPCNT.VRAMWriteBlock].purpose == VramConfiguration::LCDC) && (l < this->_dispCapCnt.capy);
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return this->_displayCaptureEnable && (vramConfiguration.banks[DISPCAPCNT.VRAMWriteBlock].purpose == VramConfiguration::LCDC) && (l < this->_dispCapCnt.capy);
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}
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void GPUEngineA::SetDisplayCaptureEnable()
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{
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this->_displayCaptureEnable = (this->_IORegisterMap->DISPCAPCNT.CaptureEnable != 0);
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}
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void GPUEngineA::ResetDisplayCaptureEnable()
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{
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IOREG_DISPCAPCNT &DISPCAPCNT = this->_IORegisterMap->DISPCAPCNT;
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if ( this->_displayCaptureEnable && vramConfiguration.banks[DISPCAPCNT.VRAMWriteBlock].purpose == VramConfiguration::LCDC )
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{
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DISPCAPCNT.CaptureEnable = 0;
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this->_displayCaptureEnable = false;
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}
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}
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bool GPUEngineA::VerifyVRAMLineDidChange(const size_t blockID, const size_t l)
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@ -6683,8 +6699,6 @@ void GPUEngineA::_LineLarge8bpp(GPUEngineCompositorInfo &compInfo)
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void GPUEngineA::LastLineProcess()
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{
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this->GPUEngineBase::LastLineProcess();
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this->_IORegisterMap->DISPCAPCNT.CaptureEnable = 0;
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DISP_FIFOreset();
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}
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@ -6961,6 +6975,16 @@ void GPUSubsystem::SetWillFrameSkip(const bool willFrameSkip)
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this->_willFrameSkip = willFrameSkip;
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}
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void GPUSubsystem::SetDisplayCaptureEnable()
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{
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this->_engineMain->SetDisplayCaptureEnable();
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}
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void GPUSubsystem::ResetDisplayCaptureEnable()
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{
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this->_engineMain->ResetDisplayCaptureEnable();
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}
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void GPUSubsystem::UpdateRenderProperties()
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{
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this->_engineMain->vramBlockOBJIndex = VRAM_NO_3D_USAGE;
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@ -1524,6 +1524,7 @@ protected:
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u16 *_VRAMCustomBlockPtr[4];
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DISPCAPCNT_parsed _dispCapCnt;
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bool _displayCaptureEnable;
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template<bool ISDEBUGRENDER, bool MOSAIC, bool WILLPERFORMWINDOWTEST, bool COLOREFFECTDISABLEDHINT, bool ISCUSTOMRENDERINGNEEDED> void _LineLarge8bpp(GPUEngineCompositorInfo &compInfo);
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@ -1565,6 +1566,8 @@ public:
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bool WillRender3DLayer();
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bool WillCapture3DLayerDirect(const size_t l);
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bool WillDisplayCapture(const size_t l);
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void SetDisplayCaptureEnable();
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void ResetDisplayCaptureEnable();
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bool VerifyVRAMLineDidChange(const size_t blockID, const size_t l);
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void LastLineProcess();
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@ -1685,6 +1688,8 @@ public:
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bool GetWillFrameSkip() const;
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void SetWillFrameSkip(const bool willFrameSkip);
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void SetDisplayCaptureEnable();
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void ResetDisplayCaptureEnable();
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void UpdateRenderProperties();
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// By default, the displays will automatically perform certain postprocessing steps on the
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@ -1480,21 +1480,20 @@ static void execHardware_hstart()
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//this should be 214, but we are going to be generous for games with tight timing
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//they shouldnt be changing any textures at 262 but they might accidentally still be at 214
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//so..
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if((CommonSettings.rigorous_timing && nds.VCount==214) || (!CommonSettings.rigorous_timing && nds.VCount==262))
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if ( (CommonSettings.rigorous_timing && nds.VCount == 214) || (!CommonSettings.rigorous_timing && nds.VCount == 262) )
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{
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gfx3d_VBlankEndSignal(frameSkipper.ShouldSkip3D());
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}
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if(nds.VCount==261)
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nds.overclock = 0;
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if(nds.VCount==263)
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if (nds.VCount == 263)
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{
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nds.VCount=0;
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nds.VCount = 0;
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GPU->SetDisplayCaptureEnable();
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}
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else if(nds.VCount==262)
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else if (nds.VCount == 262)
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{
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if(!(NDS_ARM9.waitIRQ) && nds.overclock < 200 && CommonSettings.pokehax) {
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if (!(NDS_ARM9.waitIRQ) && nds.overclock < 200 && CommonSettings.pokehax)
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{
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nds.overclock++;
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nds.VCount = 261;
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}
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@ -1504,8 +1503,14 @@ static void execHardware_hstart()
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execHardware_hstart_vblankEnd();
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}
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}
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else if(nds.VCount==192)
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else if (nds.VCount == 261)
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{
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nds.overclock = 0;
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}
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else if (nds.VCount == 192)
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{
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GPU->ResetDisplayCaptureEnable();
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//turn on vblank status bit
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T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) | 1);
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T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) | 1);
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@ -1541,7 +1546,7 @@ static void execHardware_hstart()
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//trigger hstart dmas
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triggerDma(EDMAMode_HStart);
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if(nds.VCount<192)
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if (nds.VCount < 192)
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{
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//this is hacky.
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//there is a corresponding hack in doDMA.
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@ -502,6 +502,7 @@ extern struct TCommonSettings {
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, cheatsDisable(false)
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, rigorous_timing(false)
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, advanced_timing(true)
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, pokehax(false)
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, micMode(InternalNoise)
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, spuInterpolationMode(1)
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, manualBackupType(0)
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@ -354,7 +354,7 @@ bool CommandLine::parse(int argc,char **argv)
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if(_num_cores != -1) CommonSettings.num_cores = _num_cores;
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if(_rigorous_timing) CommonSettings.rigorous_timing = true;
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if(_advanced_timing != -1) CommonSettings.advanced_timing = _advanced_timing==1;
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if(_advanced_timing != -1) CommonSettings.pokehax = _pokehax==1;
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if(_pokehax != -1) CommonSettings.pokehax = _pokehax==1;
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#ifdef HAVE_JIT
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if(_cpu_mode != -1) CommonSettings.use_jit = (_cpu_mode==1);
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