parent
38958f7998
commit
5ba5bff4d2
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@ -1183,6 +1183,24 @@ void FASTCALL _MMU_write8(u32 adr, u8 val)
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case REG_VRAMCNTD:
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if(proc == ARMCPU_ARM9)
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{
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//
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// FIXME: simply texture slot handling
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// This is a first stab and is not correct. It does
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// not handle a VRAM texture slot becoming
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// unconfigured.
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// Revisit all of VRAM control handling for future
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// release?
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//
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if ( val & 0x80) {
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if ( (val & 0x7) == 3) {
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int slot_index = (val >> 3) & 0x3;
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ARM9Mem.textureSlotAddr[slot_index] =
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&ARM9Mem.ARM9_LCD[0x20000 * (adr - REG_VRAMCNTA)];
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gpu3D->NDS_3D_VramReconfigureSignal();
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}
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}
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if (MMU_checkVRAM(adr-REG_VRAMCNTA, val) == 1) break;
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MMU_VRAMWriteBackToLCD(adr-REG_VRAMCNTA) ;
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@ -1212,24 +1230,6 @@ void FASTCALL _MMU_write8(u32 adr, u8 val)
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MMU.vram_mode[adr-REG_VRAMCNTA] = 4 | (adr-REG_VRAMCNTA) ;
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break ;
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}
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//
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// FIXME: simply texture slot handling
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// This is a first stab and is not correct. It does
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// not handle a VRAM texture slot becoming
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// unconfigured.
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// Revisit all of VRAM control handling for future
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// release?
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//
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if ( val & 0x80) {
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if ( (val & 0x7) == 3) {
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int slot_index = (val >> 3) & 0x3;
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ARM9Mem.textureSlotAddr[slot_index] =
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&ARM9Mem.ARM9_LCD[0x20000 * (adr - REG_VRAMCNTA)];
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gpu3D->NDS_3D_VramReconfigureSignal();
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}
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}
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MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTA,val) ;
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}
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break;
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